A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem

Author(s):  
Tong Jing ◽  
Ling Zhang ◽  
Jinghong Liang ◽  
Jingyu Xu ◽  
Xianlong Hong ◽  
...  
2019 ◽  
Vol 142 (6) ◽  
Author(s):  
Haiguang Liao ◽  
Wentai Zhang ◽  
Xuliang Dong ◽  
Barnabas Poczos ◽  
Kenji Shimada ◽  
...  

Abstract Global routing has been a historically challenging problem in the electronic circuit design, where the challenge is to connect a large and arbitrary number of circuit components with wires without violating the design rules for the printed circuit boards or integrated circuits. Similar routing problems also exist in the design of complex hydraulic systems, pipe systems, and logistic networks. Existing solutions typically consist of greedy algorithms and hard-coded heuristics. As such, existing approaches suffer from a lack of model flexibility and usually fail to solve sub-problems conjointly. As an alternative approach, this work presents a deep reinforcement learning method for solving the global routing problem in a simulated environment. At the heart of the proposed method is deep reinforcement learning that enables an agent to produce a policy for routing based on the variety of problems, and it is presented with leveraging the conjoint optimization mechanism of deep reinforcement learning. Conjoint optimization mechanism is explained and demonstrated in detail; the best network structure and the parameters of the learned model are explored. Based on the fine-tuned model, routing solutions and rewards are presented and analyzed. The results indicate that the approach can outperform the benchmark method of a sequential A* method, suggesting a promising potential for deep reinforcement learning for global routing and other routing or path planning problems in general. Another major contribution of this work is the development of a global routing problem sets generator with the ability to generate parameterized global routing problem sets with different size and constraints, enabling evaluation of different routing algorithms and the generation of training datasets for future data-driven routing approaches.


Author(s):  
Zhen Cao ◽  
Tom Tong Jing ◽  
Jinjun Xiong ◽  
Yu Hu ◽  
Zhe Feng ◽  
...  

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Subhrapratim Nath ◽  
Jamuna Kanta Sing ◽  
Subir Kumar Sarkar

Purpose Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO). Design/methodology/approach This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark. Findings This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits. Practical implications This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms. Originality/value This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.


VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-13 ◽  
Author(s):  
Logan Rakai ◽  
Laleh Behjat ◽  
Shawki Areibi ◽  
Tamas Terlaky

Routing in nanometer nodes creates an elevated level of importance for low-congestion routing. At the same time, advances in mathematical programming have increased the power to solve complex problems, such as the routing problem. Hence, new routing methods need to be developed that can combine advanced mathematical programming and modeling techniques to provide low-congestion solutions. In this paper, a hierarchical mathematical programming-based global routing technique that considers congestion is proposed. The main contributions presented in this paper include (i) implementation of congestion estimation based on actual routing solutions versus purely probabilistic techniques, (ii) development of a congestion-based hierarchy for solving the global routing problem, and (iii) generation of a robust framework for solving the routing problem using mathematical programming techniques. Experimental results illustrate that the proposed global router is capable of reducing congestion and overflow by as much as 36% compared to the state-of-the-art mathematical programming models.


Author(s):  
S. Thakur ◽  
Yao-Wen Chang ◽  
D.F. Wong ◽  
S. Muthukrishnan

Author(s):  
Sudipta Ghosh ◽  
Subhrapratim Nath ◽  
Rajarshi Biswas ◽  
P. Venkateswaran ◽  
Jamuna Kanta Sing ◽  
...  

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