Power Consumption Due to Data Movement in Distributed Programming Models

2014 ◽  
pp. 366-378 ◽  
Author(s):  
Siddhartha Jana ◽  
Oscar Hernandez ◽  
Stephen Poole ◽  
Barbara Chapman
Keyword(s):  
Power Consumption ◽  
Programming Models ◽  
Distributed Programming ◽  
Data Movement

scholarly journals Striping input feature map cache for reducing off-chip memory traffic in CNN accelerators

2020 ◽  
Vol 12 (2) ◽  
pp. 116-121
Author(s):  
Rastislav Struharik ◽  
Vuk Vranjković
Keyword(s):  
Power Consumption ◽  
Data Reuse ◽  
Memory Architecture ◽  
Cache Memories ◽  
Data Movement ◽  
Feature Map ◽  
Input Feature ◽  
On Chip ◽  
Memory Resources ◽  
Embedded Applications

Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications. Specific CNN computes patterns offer a possibility of significant data reuse, leading to the idea of using specialized on-chip cache memories which enable a significant improvement in power consumption. However, due to the unique caching pattern present within CNNs, standard cache memories would not be efficient. In this paper, a novel on-chip cache memory architecture, based on the idea of input feature map striping, is proposed, which requires significantly less on-chip memory resources compared to previously proposed solutions. Experiment results show that the proposed cache architecture can reduce on-chip memory size by a factor of 16 or more, while increasing power consumption no more than 15%, compared to some of the previously proposed solutions.

scholarly journals Accelerating Spark-Based Applications with MPI and OpenACC

Complexity ◽  
2021 ◽  
Vol 2021 ◽  
pp. 1-17
Author(s):  
Saeed Alshahrani ◽  
Waleed Al Shehri ◽  
Jameel Almalki ◽  
Ahmed M. Alghamdi ◽  
Abdullah M. Alammari
Keyword(s):  
Big Data ◽  
Power Consumption ◽  
Parallel Programming ◽  
Graphics Processing Units ◽  
Message Passing Interface ◽  
Programming Model ◽  
Programming Models ◽  
Mapping Technique ◽  
Big Data Applications ◽  
Parallel Programming Models

The amount of data produced in scientific and commercial fields is growing dramatically. Correspondingly, big data technologies, such as Hadoop and Spark, have emerged to tackle the challenges of collecting, processing, and storing such large-scale data. Unfortunately, big data applications usually have performance issues and do not fully exploit a hardware infrastructure. One reason is that applications are developed using high-level programming languages that do not provide low-level system control in terms of performance of highly parallel programming models like message passing interface (MPI). Moreover, big data is considered a barrier of parallel programming models or accelerators (e.g., CUDA and OpenCL). Therefore, the aim of this study is to investigate how the performance of big data applications can be enhanced without sacrificing the power consumption of a hardware infrastructure. A Hybrid Spark MPI OpenACC (HSMO) system is proposed for integrating Spark as a big data programming model, with MPI and OpenACC as parallel programming models. Such integration brings together the advantages of each programming model and provides greater effectiveness. To enhance performance without sacrificing power consumption, the integration approach needs to exploit the hardware infrastructure in an intelligent manner. For achieving this performance enhancement, a mapping technique is proposed that is built based on the application’s virtual topology as well as the physical topology of the undelaying resources. To the best of our knowledge, there is no existing method in big data applications related to utilizing graphics processing units (GPUs), which are now an essential part of high-performance computing (HPC) as a powerful resource for fast computation.

An Analysis of Distributed Programming Models and Frameworks for Large-scale Graph Processing

2020 ◽  
pp. 1-9 ◽  
Author(s):  
Alejandro Corbellini ◽  
Daniela Godoy ◽  
Cristian Mateos ◽  
Silvia Schiaffino ◽  
Alejandro Zunino
Keyword(s):  
Large Scale ◽  
Programming Models ◽  
Distributed Programming ◽  
Graph Processing

scholarly journals The MapReduce Model on Cascading Platform for Frequent Itemset Mining

2018 ◽  
Vol 12 (2) ◽  
pp. 149
Author(s):  
Nur Rokhman ◽  
Amelia Nursanti
Keyword(s):  
Large Scale ◽  
Frequent Itemset ◽  
Frequent Itemset Mining ◽  
Programming Models ◽  
Distributed Programming ◽  
Itemset Mining ◽  
Large Scale Data ◽  
Mapreduce Model ◽  
Large Scale Data Processing ◽  
Scale Data

The implementation of parallel algorithms is very interesting research recently. Parallelism is very suitable to handle large-scale data processing. MapReduce is one of the parallel and distributed programming models. The implementation of parallel programming faces many difficulties. The Cascading gives easy scheme of Hadoop system which implements MapReduce model.Frequent itemsets are most often appear objects in a dataset. The Frequent Itemset Mining (FIM) requires complex computation. FIM is a complicated problem when implemented on large-scale data. This paper discusses the implementation of MapReduce model on Cascading for FIM. The experiment uses the Amazon dataset product co-purchasing network metadata.The experiment shows the fact that the simple mechanism of Cascading can be used to solve FIM problem. It gives time complexity O(n), more efficient than the nonparallel which has complexity O(n2/m).

scholarly journals New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 368 ◽  
Author(s):  
Giulia Santoro ◽  
Giovanna Turvani ◽  
Mariagrazia Graziano
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Point Of View ◽  
Oxide Semiconductor ◽  
Strong Impact ◽  
Technological Advancement ◽  
Data Movement ◽  
Memory Wall

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

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