scholarly journals New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 368 ◽  
Author(s):  
Giulia Santoro ◽  
Giovanna Turvani ◽  
Mariagrazia Graziano
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Point Of View ◽  
Oxide Semiconductor ◽  
Strong Impact ◽  
Technological Advancement ◽  
Data Movement ◽  
Memory Wall

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal–oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm.

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

scholarly journals Online Nonlinear Error Compensation Circuit Based on Neural Networks

Machines ◽  
2021 ◽  
Vol 9 (8) ◽  
pp. 151
Author(s):  
Zhenyi Gao ◽  
Bin Zhou ◽  
Chunge Ju ◽  
Qi Wei ◽  
Xinxi Zhang ◽  
...  
Keyword(s):  
Machine Learning ◽  
Neural Networks ◽  
Power Consumption ◽  
Inertial Sensors ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Signal Frequency ◽  
Small Scale ◽  
Compensation Circuit

Nonlinear errors of sensor output signals are common in the field of inertial measurement and can be compensated with statistical models or machine learning models. Machine learning solutions with large computational complexity are generally offline or implemented on additional hardware platforms, which are difficult to meet the high integration requirements of microelectromechanical system inertial sensors. This paper explored the feasibility of an online compensation scheme based on neural networks. In the designed solution, a simplified small-scale network is used for modeling, and the peak-to-peak value and standard deviation of the error after compensation are reduced to 17.00% and 16.95%, respectively. Additionally, a compensation circuit is designed based on the simplified modeling scheme. The results show that the circuit compensation effect is consistent with the results of the algorithm experiment. Under SMIC 180 nm complementary metal-oxide semiconductor (CMOS) technology, the circuit has a maximum operating frequency of 96 MHz and an area of 0.19 mm2. When the sampling signal frequency is 800 kHz, the power consumption is only 1.12 mW. This circuit can be used as a component of the measurement and control system on chip (SoC), which meets real-time application scenarios with low power consumption requirements.

scholarly journals Design and Implementation of High Performance and Low Power Mixed Logic Line Decoders

2019 ◽  
Vol 8 (6S4) ◽  
pp. 635-640
Keyword(s):  
High Performance ◽  
Data Transfer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Analog To Digital ◽  
Delay Performance ◽  
And Performance ◽  
Almost All

The decoders are widely used in the logical circuits, data transfer circuits and analog to digital conversions. A mixed logic design methods for the line decoders are used to combining the transmission gate logic, pass transistor logic, and complementary metal-oxide semiconductor (CMOS) technology provides desired operation and performance. A novel topology is presented for the 2 to 4 decoder requires a fourteen transistor topology aiming on reducing the transistor count and operating power and a fifteen transistor topology aiming on high power and low delay performance. The standard and inverting decoders are designed in each of the case, gives a total of four new designs circuits. All the proposed decoders have compact transistor count compared to their conservative CMOS technologies. Finally, a variety of proposed designs present a noteworthy improvement in operating power and propagation delay, outperforming CMOS in almost all the cases.

An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

scholarly journals Design Architectures of the CMOS Power Amplifier for 2.4 GHz ISM Band Applications: An Overview

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 477 ◽  
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md Torikul Islam Badal ◽  
Mamun Bin Ibne Reaz ◽  
Maria Liz Crespo ◽  
Andres Cicuttin
Keyword(s):  
Output Power ◽  
High Performance ◽  
High Efficiency ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Hot Electron ◽  
Oxide Breakdown ◽  
Rf Signals ◽  
Hot Electron Effect

Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency (RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the required output power. The signal is amplified to make it sufficiently high for the transmitter to propagate the required distance to the receiver. Attempted advancements of PA have focused on attaining high-performance RF signals for transmitters. Such PAs are expected to require low power consumption while producing a relatively high output power with a high efficiency. However, current PA designs in nanometer and micrometer complementary metal–oxide semiconductor (CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect. A well-defined architecture, including a linear and simple functional block synthesis, is critical in designing CMOS PA for various applications. This article describes the different state-of-the art design architectures of CMOS PA, including their circuit operations, and analyzes the performance of PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

scholarly journals High Performance Seesaw Torsional CMOS-MEMS Relay Using Tungsten VIA Layer

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 579 ◽  
Author(s):  
Martín Riverola ◽  
Francesc Torres ◽  
Arantxa Uranga ◽  
Núria Barniol
Keyword(s):  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Life Time ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Mechanical Contact ◽  
Contact Materials ◽  
Monolithically Integrated ◽  
Cmos Mems ◽  
Mechanical Logic

In this paper, a seesaw torsional relay monolithically integrated in a standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology is presented. The seesaw relay is fabricated using the Back-End-Of-Line (BEOL) layers available, specifically using the tungsten VIA3 layer of a 0.35 μm CMOS technology. Three different contact materials are studied to discriminate which is the most adequate as a mechanical relay. The robustness of the relay is proved, and its main characteristics as a relay for the three different contact interfaces are provided. The seesaw relay is capable of a double hysteretic switching cycle, providing compactness for mechanical logic processing. The low contact resistance achieved with the TiN/W mechanical contact with high cycling life time is competitive in comparison with the state-of-the art.

A Review of QCA Nanotechnology as an Alternate to CMOS

2021 ◽  
Vol 17 ◽  
Author(s):  
Syed Farah Naz ◽  
Sadat Riyaz ◽  
Vijay Kumar Sharma
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Extensive Study ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Data Movement ◽  
Mos Device

Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical limitations of the MOS device. QCA is a dynamic computational transistor paradigm that addresses device density, power, operating frequency and interconnection problems. It requires an extensive study to know the fundamentals of logic implementation. Objective: Immense research and experiments due same vigor led to the evolving nanotechnology and a feasible alternative to complementary metal oxide semiconductor (CMOS) technology. A comprehensive study is presented in the paper to enhance the basics of QCA technology and the way of implementation of the logic circuits. Different existing circuits using QCA technology are discussed and compared for different parameters. Methods: Scaling the devices can reduce the power consumption of the MOS device. Quantum dots are nanostructures made from semi-conductive conventional materials. It is possible to model these constructions as 3-dimensional (3D) quantum energy wells. Logical operations and data movement are performed using Columbic interaction between nearby QCA cells instead of current flow. Results: The focus of this review paper is to study the trends which have been proposed and compared the designs for various digital circuits. The performance of different circuits such as XOR, adder, reversible gates and flip-flops are provided. Different logic circuits are compared on the parameters such as cell count, area and latency. At least 10 QCA cells are used for the XOR gate with 1 clock latency. Minimum 44 QCA cells are required to make a full adder with 1.25 clock latency.

scholarly journals A new design for 4-bit RCA using Quantum Cellular Automata Technology

2021 ◽  
Author(s):  
Saeid Seyedi ◽  
Behrouz Pourghebleh
Keyword(s):  
Cellular Automata ◽  
Power Consumption ◽  
Cell Count ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Quantum Cellular Automata ◽  
Ripple Carry Adder ◽  
Efficient Alternative

Abstract Since the scaling of transistors is growing rapidly, the need for an efficient alternative for the Complementary Metal-Oxide-Semiconductor (CMOS) technology to obtain further and extra processes in the circuits has known as the main problem. Over the last decade, Quantum-dot Cellular Automata (QCA) technology due to its excellent potential in developing designs with low-power consumption, high-speed, and high-density has been recognized as a suitable replacement to CMOS technology. In this regard, lowering the number of gates, the amount of cell count, and delay has been emphasized in the design of QCA-based circuits. Adders as the main unit in logic circuits and digital arithmetic play an important role in constructing various effective QCA designs. In this regard, Ripple Carry Adder (RCA) is a simple form of adders and due to its remarkable features can be useful to reach circuits with the minimum required area and power consumption. Therefore, in this study, a new design for RCA in QCA technology is recommended to reduce the cell count, amend the complexity, and decrease the latency. To verify the correctness of the suggested circuit, the QCADesigner version 2.0.3 as a well known simulator has been used. The evaluation results confirm that the proposed design has approximately 28.6% improvement in cell count in comparison to the state-of-the-art four-bit coplanar RCA designs in QCA technology. Also, the obtained results designate the effectiveness of the advised plan.

scholarly journals A Near-Infrared CMOS Silicon Avalanche Photodetector with Ultra-Low Temperature Coefficient of Breakdown Voltage

Micromachines ◽  
2021 ◽  
Vol 13 (1) ◽  
pp. 47
Author(s):  
Daoqun Liu ◽  
Tingting Li ◽  
Bo Tang ◽  
Peng Zhang ◽  
Wenwu Wang ◽  
...  
Keyword(s):  
Temperature Coefficient ◽  
Breakdown Voltage ◽  
High Performance ◽  
Near Infrared ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Infrared Light ◽  
Manufacturing Cost ◽  
Light Detection

Silicon avalanche photodetector (APD) plays a very important role in near-infrared light detection due to its linear controllable gain and attractive manufacturing cost. In this paper, a silicon APD with punch-through structure is designed and fabricated by standard 0.5 μm complementary metal oxide semiconductor (CMOS) technology. The proposed structure eliminates the requirements for wafer-thinning and the double-side metallization process by most commercial Si APD products. The fabricated device shows very low level dark current of several tens Picoamperes and ultra-high multiplication gain of ~4600 at near-infrared wavelength. The ultra-low extracted temperature coefficient of the breakdown voltage is 0.077 V/K. The high performance provides a promising solution for near-infrared weak light detection.

scholarly journals Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

2022 ◽  
Vol 10 (1) ◽  
pp. 732-737
Author(s):  
Prakash Sharma
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Noise Power ◽  
Ring Oscillators ◽  
Voltage Controlled Oscillator

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

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