FPGA Implementation of Neuron Model Using Piecewise Nonlinear Function on Double-Precision Floating-Point Format

2016 ◽  
pp. 620-629
Author(s):  
Satoshi Kawamura ◽  
Masato Saito ◽  
Hitoaki Yoshida
Keyword(s):  
Neuron Model ◽  
Nonlinear Function ◽  
Fpga Implementation ◽  
Floating Point ◽  
Double Precision

scholarly journals Research on IEEE 754 Standard Single Precision Floating Point Multipliers Designed using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2990-2993
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Single Precision ◽  
Vedic Mathematics ◽  
Quadruple Precision

Duplication of the coasting element numbers is the big activity in automated signal handling. So the exhibition of drifting problem multipliers count on a primary undertaking in any computerized plan. Coasting factor numbers are spoken to utilizing IEEE 754 modern day in single precision(32-bits), Double precision(sixty four-bits) and Quadruple precision(128-bits) organizations. Augmentation of those coasting component numbers can be completed via using Vedic generation. Vedic arithmetic encompass sixteen wonderful calculations or Sutras. Urdhva Triyagbhyam Sutra is most usually applied for growth of twofold numbers. This paper indicates the compare of tough work finished via exceptional specialists in the direction of the plan of IEEE 754 ultra-modern-day unmarried accuracy skimming thing multiplier the usage of Vedic technological statistics.

A FPGA Implementation of An Open-Source Floating-Point Computation System

2005 ◽  
Author(s):  
C. Brunelli ◽  
F. Garzia ◽  
J. Nurmi ◽  
C. Mucci ◽  
F. Campi ◽  
...  
Keyword(s):  
Open Source ◽  
Fpga Implementation ◽  
Floating Point ◽  
Floating Point Computation

The FPGA Implementation of Single-Precision Floating-Point Adder

2014 ◽  
Vol 1008-1009 ◽  
pp. 668-671
Author(s):  
Hai Ke Liu ◽  
Xin Gna Kang ◽  
Shun Wang
Keyword(s):  
Real Number ◽  
Fpga Implementation ◽  
Floating Point ◽  
Single Precision ◽  
Operation Process ◽  
Storage Format ◽  
Process Ability

A design of single precision floating point adder based on FPGA is presented,by analysing the form of real number formed on IEEE 754 and the storage format of IEEE 754 single-precision floating point,the addition arithmetic process which is easy to realized by using FPGA is put forward,the split of module based on the arithmetic process facilitates the realization of pipeline designing,so the single precision floating point adder introduce by this paper has powerful operation process ability.

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