FPGA Implementation of Double Precision Floating Point Arithmetic Unit

2015 ◽  
Author(s):  
Prabhjot Kaur ◽  
◽  
Ankur Sharma ◽  
Raminder Preet Pal Singh ◽  
◽  
...  
Keyword(s):  
Fpga Implementation ◽  
Floating Point ◽  
Double Precision ◽  
Arithmetic Unit ◽  
Floating Point Arithmetic ◽  
Point Arithmetic

Double Precision Floating Point Arithmetic Unit Implementation- A Review

2015 ◽  
Vol V4 (07) ◽  
Author(s):  
Prabjot Kaur ◽  
Rajiv Ranjan ◽  
Raminder Preet Pal Singh ◽  
Onkar Singh ◽  
Keyword(s):  
Floating Point ◽  
Double Precision ◽  
Arithmetic Unit ◽  
Floating Point Arithmetic ◽  
Point Arithmetic

Operational Single-Precision Earth-System Modelling at ECMWF

2021 ◽  
Author(s):  
Sam Hatfield ◽  
Kristian Mogensen ◽  
Peter Dueben ◽  
Nils Wedi ◽  
Michail Diamantakis
Keyword(s):  
Atmospheric Model ◽  
Floating Point ◽  
System Modelling ◽  
Double Precision ◽  
Earth System ◽  
Single Precision ◽  
System Models ◽  
Floating Point Arithmetic ◽  
Point Arithmetic ◽  
Earth System Models

<p>Earth-System models traditionally use double-precision, 64 bit floating-point numbers to perform arithmetic. According to orthodoxy, we must use such a relatively high level of precision in order to minimise the potential impact of rounding errors on the physical fidelity of the model. However, given the inherently imperfect formulation of our models, and the computational benefits of lower precision arithmetic, we must question this orthodoxy. At ECMWF, a single-precision, 32 bit variant of the atmospheric model IFS has been undergoing rigorous testing in preparation for operations for around 5 years. The single-precision simulations have been found to have effectively the same forecast skill as the double-precision simulations while finishing in 40% less time, thanks to the memory and cache benefits of single-precision numbers. Following these positive results, other modelling groups are now also considering single-precision as a way to accelerate their simulations.</p><p>In this presentation I will present the rationale behind the move to lower-precision floating-point arithmetic and up-to-date results from the single-precision atmospheric model at ECMWF, which will be operational imminently. I will then provide an update on the development of the single-precision ocean component at ECMWF, based on the NEMO ocean model, including a verification of quarter-degree simulations. I will also present new results from running ECMWF's coupled atmosphere-ocean-sea-ice-wave forecasting system entirely with single-precision. Finally I will discuss the feasibility of even lower levels of precision, like half-precision, which are now becoming available through GPU- and ARM-based systems such as Summit and Fugaku, respectively. The use of reduced-precision floating-point arithmetic will be an essential consideration for developing high-resolution, storm-resolving Earth-System models.</p>

Implementation of Low Power Pipelined 64-bit RISC Processor with Unbiased FPU on CPLD

2016 ◽  
Vol 5 (2) ◽  
pp. 118
Author(s):  
J. Vijay Kumar ◽  
B. Naga Raju ◽  
M. Vasu Babu ◽  
T. Ramanjappa
Keyword(s):  
Low Power ◽  
Arithmetic Operation ◽  
Floating Point ◽  
Double Precision ◽  
Verilog Hdl ◽  
Logical Function ◽  
Floating Point Arithmetic ◽  
Risc Processor ◽  
Operation Results ◽  
Point Arithmetic

This article represents the implementation of low power pipelined 64-bit RISC processor on Altera MAXV CPLD device.  The design is verified for arithmetic operations of both fixed and floating point numbers, branch and logical function of RISC processor. For all the jump instruction, the processor architecture will automatically flush the data in the pipeline, so as to avoid any misbehavior. This processor contains FPU unit, which supports double precision IEEE-754 format operations very accurately. The simulation results have been verified by using ModelSim software. The ALU operations and double precision floating point arithmetic operation results are displayed on 7-Segments. The necessary code is written in Verilog HDL.

Implementation of Embedded Floating Point Arithmetic Units on FPGA

2014 ◽  
Vol 550 ◽  
pp. 126-136
Author(s):  
N. Ramya Rani
Keyword(s):  
High Speed ◽  
High Performance ◽  
Floating Point ◽  
Double Precision ◽  
Embedded Computing ◽  
Floating Point Arithmetic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Arithmetic Units ◽  
Point Arithmetic

:Floating point arithmetic plays a major role in scientific and embedded computing applications. But the performance of field programmable gate arrays (FPGAs) used for floating point applications is poor due to the complexity of floating point arithmetic. The implementation of floating point units on FPGAs consumes a large amount of resources and that leads to the development of embedded floating point units in FPGAs. Embedded applications like multimedia, communication and DSP algorithms use floating point arithmetic in processing graphics, Fourier transformation, coding, etc. In this paper, methodologies are presented for the implementation of embedded floating point units on FPGA. The work is focused with the aim of achieving high speed of computations and to reduce the power for evaluating expressions. An application that demands high performance floating point computation can achieve better speed and density by incorporating embedded floating point units. Additionally this paper describes a comparative study of the design of single precision and double precision pipelined floating point arithmetic units for evaluating expressions. The modules are designed using VHDL simulation in Xilinx software and implemented on VIRTEX and SPARTAN FPGAs.

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