A Low-Power Encoding Scheme for GigaByte Video Interfaces

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-30205-6_8 ◽

2004 ◽

pp. 58-68

Author(s):

Sabino Salerno ◽

Enrico Macii ◽

Massimo Poncino

Keyword(s):

Low Power ◽

Encoding Scheme

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Dual low-power and crosstalk immune encoding scheme for on-chip data buses

Electronics Letters ◽

10.1049/el:20030934 ◽

2003 ◽

Vol 39 (20) ◽

pp. 1436 ◽

Author(s):

Z. Khan ◽

A.T. Erdogan ◽

T. Arslan

Keyword(s):

Low Power ◽

Encoding Scheme ◽

Chip Data ◽

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A Novel Encoding Scheme for Low Power in Network on Chip Links

2012 25th International Conference on VLSI Design ◽

10.1109/vlsid.2012.80 ◽

2012 ◽

Author(s):

Deepa N. Sarma ◽

G. Lakshminarayanan ◽

K.V.R. Suryakiran Chavali

Keyword(s):

Low Power ◽

Network On Chip ◽

Encoding Scheme ◽

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Coupling-driven signal encoding scheme for low-power interface design

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140) ◽

10.1109/iccad.2000.896492 ◽

2002 ◽

Author(s):

Ki-Wook Kim ◽

Kwang-Hyun-Baek ◽

N. Shanbhag ◽

C.L. Liu ◽

Sung-Mo Kang

Keyword(s):

Low Power ◽

Interface Design ◽

Encoding Scheme ◽

Signal Encoding ◽

Low Power Interface

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A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-30205-6_60 ◽

2004 ◽

pp. 585-592 ◽

Author(s):

Zahid Khan ◽

Tughrul Arslan ◽

Ahmet T. Erdogan

Keyword(s):

Low Power ◽

System On Chip ◽

Encoding Scheme ◽

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Multiple-valued multiple-rail encoding scheme for low-power asynchronous communication

Proceedings. 34th International Symposium on Multiple-Valued Logic ◽

10.1109/ismvl.2004.1319914 ◽

2004 ◽

Author(s):

T. Takahashi ◽

T. Hanyu

Keyword(s):

Low Power ◽

Asynchronous Communication ◽

Encoding Scheme

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Low power system on chip bus encoding scheme with crosstalk noise reduction capability

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20050152 ◽

2006 ◽

Vol 153 (2) ◽

pp. 101 ◽

Author(s):

Z. Khan ◽

T. Arslan ◽

A.T. Erdogan

Keyword(s):

Power System ◽

Low Power ◽

Noise Reduction ◽

System On Chip ◽

Crosstalk Noise ◽

Encoding Scheme ◽

Low Power System ◽

Bus Encoding ◽

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A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission

Lecture Notes in Computer Science - Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/3-540-45716-x_34 ◽

2002 ◽

pp. 342-352 ◽

Author(s):

Claudia Kretzschmar ◽

Robert Siegmund ◽

Dietmar Müller

Keyword(s):

Low Power ◽

Data Transmission ◽

Encoding Scheme ◽

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Low power multi-chains encoding scheme for SoC in low-cost environment

2009 International Test Conference ◽

10.1109/test.2009.5355633 ◽

2009 ◽

Author(s):

Po-Han Wu ◽

Jiann-Chyi Rau

Keyword(s):

Low Power ◽

Low Cost ◽

Encoding Scheme

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An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1692937 ◽

2006 ◽

Author(s):

S. Komatsu ◽

M. Fujita

Keyword(s):

Low Power ◽

Encoding Scheme ◽

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A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion

The Journal of Korean Institute of Communications and Information Sciences ◽

10.7840/kics.2011.36b.12.1548 ◽

2011 ◽

Vol 36 (12B) ◽

pp. 1548-1555

Author(s):

Youn-Jin Lee ◽

Qu Shidi ◽

Young-Chul Kim

Keyword(s):

Low Power ◽

Encoding Scheme ◽

Power Bus ◽

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