An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1692937 ◽

2006 ◽

Author(s):

S. Komatsu ◽

M. Fujita

Keyword(s):

Low Power ◽

Encoding Scheme ◽

Download Full-text

Low power system on chip bus encoding scheme with crosstalk noise reduction capability

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20050152 ◽

2006 ◽

Vol 153 (2) ◽

pp. 101 ◽

Author(s):

Z. Khan ◽

T. Arslan ◽

A.T. Erdogan

Keyword(s):

Power System ◽

Low Power ◽

Noise Reduction ◽

System On Chip ◽

Crosstalk Noise ◽

Encoding Scheme ◽

Low Power System ◽

Bus Encoding ◽

Download Full-text

A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission

Lecture Notes in Computer Science - Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/3-540-45716-x_34 ◽

2002 ◽

pp. 342-352 ◽

Author(s):

Claudia Kretzschmar ◽

Robert Siegmund ◽

Dietmar Müller

Keyword(s):

Low Power ◽

Data Transmission ◽

Encoding Scheme ◽

Download Full-text

A New Low-Power Bus Encoding Scheme Using Bus-Invert Logic Conversion

The Journal of Korean Institute of Communications and Information Sciences ◽

10.7840/kics.2011.36b.12.1548 ◽

2011 ◽

Vol 36 (12B) ◽

pp. 1548-1555

Author(s):

Youn-Jin Lee ◽

Qu Shidi ◽

Young-Chul Kim

Keyword(s):

Low Power ◽

Encoding Scheme ◽

Power Bus ◽

Download Full-text

Probabilistic Modeling of Frequent Value Bus Encoding Scheme for Low Power Computation

2009 IEEE International Advance Computing Conference ◽

10.1109/iadcc.2009.4809115 ◽

2009 ◽

Author(s):

Kamal K Mehta ◽

M. Kowar ◽

H. R. Sharma

Keyword(s):

Low Power ◽

Probabilistic Modeling ◽

Encoding Scheme ◽

Download Full-text

Narrow bus encoding for low power systems

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106) ◽

10.1109/aspdac.2000.835099 ◽

2002 ◽

Author(s):

Youngsoo Shin ◽

Kiyoung Choi

Keyword(s):

Power Systems ◽

Low Power ◽

Download Full-text

Low-power bus encoding using an adaptive hybrid algorithm

2006 43rd ACM/IEEE Design Automation Conference ◽

10.1109/dac.2006.229425 ◽

2006 ◽

Author(s):

A.R. Brahmbhatt ◽

Jingyi Zhang ◽

Qing Wu ◽

Qinru Qiu

Keyword(s):

Low Power ◽

Hybrid Algorithm ◽

Power Bus ◽

Download Full-text

A Low-Power Encoding Scheme for GigaByte Video Interfaces

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-30205-6_8 ◽

2004 ◽

pp. 58-68

Author(s):

Sabino Salerno ◽

Enrico Macii ◽

Massimo Poncino

Keyword(s):

Low Power ◽

Encoding Scheme

Download Full-text

A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2007.907260 ◽

2007 ◽

Vol 26 (12) ◽

pp. 2222-2227 ◽

Author(s):

Wen-Wen Hsieh ◽

Po-Yuan Chen ◽

Chun-Yao Wang ◽

TingTing Hwang

Keyword(s):

High Performance ◽

Processor Design ◽

Encoding Scheme ◽

Bus Encoding ◽

Crosstalk Elimination

Download Full-text

Dual low-power and crosstalk immune encoding scheme for on-chip data buses

Electronics Letters ◽

10.1049/el:20030934 ◽

2003 ◽

Vol 39 (20) ◽

pp. 1436 ◽

Author(s):

Z. Khan ◽

A.T. Erdogan ◽

T. Arslan

Keyword(s):

Low Power ◽

Encoding Scheme ◽

Chip Data ◽

Download Full-text

Irredundant address bus encoding techniques based on adaptive codebooks for low power

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC ◽

10.1145/1119772.1119775 ◽

2003 ◽

Author(s):

Satoshi Komatsu ◽

Masahiro Fujita

Keyword(s):

Low Power ◽

Download Full-text