Reconfigurable MAC-Based Architecture for Parallel Hardware Implementation on FPGAs of Artificial Neural Networks Using Fractional Fixed Point Representation

2009 ◽  
pp. 475-484
Author(s):  
Rodrigo Martins da Silva ◽  
Nadia Nedjah ◽  
Luiza de Macedo Mourelle
Keyword(s):  
Neural Networks ◽  
Fixed Point ◽  
Artificial Neural Networks ◽  
Hardware Implementation ◽  
Point Representation ◽  
Artificial Neural

Parallel Hardware for Artificial Neural Networks Using Fixed Floating Point Representation

2011 ◽  
pp. 295-308
Author(s):  
Nadia Nedjah ◽  
Rodrigo Martins da Silva ◽  
Luiza de Macedo Mourelle
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Activation Function ◽  
Floating Point ◽  
Weighted Sum ◽  
Design Environment ◽  
Silicon Area ◽  
Point Representation ◽  
Artificial Neural ◽  
Mathematical Computation

Artificial Neural Networks (ANNs) is a well known bio-inspired model that simulates human brain capabilities such as learning and generalization. ANNs consist of a number of interconnected processing units, wherein each unit performs a weighted sum followed by the evaluation of a given activation function. The involved computation has a tremendous impact on the implementation efficiency. Existing hardware implementations of ANNs attempt to speed up the computational process. However, these implementations require a huge silicon area that makes it almost impossible to fit within the resources available on a state-of-the-art FPGAs. In this chapter, a hardware architecture for ANNs that takes advantage of the dedicated adder blocks, commonly called MACs, to compute both the weighted sum and the activation function is devised. The proposed architecture requires a reduced silicon area considering the fact that the MACs come for free as these are FPGA’s built-in cores. Our system uses integer (fixed point) mathematics and operates with fractions to represent real numbers. Hence, floating point representation is not employed and any mathematical computation of the ANN hardware is based on combinational circuitry (performing only sums and multiplications). The hardware is fast because it is massively parallel. Besides, the proposed architecture can adjust itself on-the-fly to the user-defined configuration of the neural network, i.e., the number of layers and neurons per layer of the ANN can be settled with no extra hardware changes. This is a very nice characteristic in robot-like systems considering the possibility of the same hardware may be exploited in different tasks. The hardware also requires another system (a software) that controls the sequence of the hardware computation and provides inputs, weights and biases for the ANN in hardware. Thus, a co-design environment is necessary.

The Faulty Behavior of Feedforward Neural Networks with Hard-Limiting Activation Function

1997 ◽  
Vol 9 (5) ◽  
pp. 1109-1126
Author(s):  
Zhiyu Tian ◽  
Ting-Ting Y. Lin ◽  
Shiyuan Yang ◽  
Shibai Tong
Keyword(s):  
Neural Networks ◽  
Monte Carlo ◽  
Artificial Neural Networks ◽  
Monte Carlo Simulations ◽  
Hardware Implementation ◽  
Fault Tolerant ◽  
Feedforward Neural Networks ◽  
Activation Function ◽  
Artificial Neural

With the progress in hardware implementation of artificial neural networks, the ability to analyze their faulty behavior has become increasingly important to their diagnosis, repair, reconfiguration, and reliable application. The behavior of feedforward neural networks with hard limiting activation function under stuck-at faults is studied in this article. It is shown that the stuck-at-M faults have a larger effect on the network's performance than the mixed stuck-at faults, which in turn have a larger effect than that of stuck-at-0 faults. Furthermore, the fault-tolerant ability of the network decreases with the increase of its size for the same percentage of faulty interconnections. The results of our analysis are validated by Monte-Carlo simulations.

Compact yet efficient hardware implementation of artificial neural networks with customized topology

2012 ◽  
Vol 39 (10) ◽  
pp. 9191-9206 ◽  
Author(s):  
Nadia Nedjah ◽  
Rodrigo Martins da Silva ◽  
Luiza de Macedo Mourelle
Keyword(s):  
Neural Networks ◽  
Artificial Neural Networks ◽  
Hardware Implementation ◽  
Artificial Neural
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