A High-Performance Framework for Instruction-Set Simulator

2012 ◽  
pp. 9-14 ◽  
Author(s):  
Zhu Hao ◽  
Peng Chu ◽  
Tiejun Zhang ◽  
Donghui Wang ◽  
Chaohuan Hou
Keyword(s):  
High Performance ◽  
Instruction Set ◽  
Performance Framework

scholarly journals Back-end porting of FT_MX based on LLVM compilation architecture

2021 ◽  
Vol 336 ◽  
pp. 04018
Author(s):  
Ping Deng ◽  
Xiaolong Zhu ◽  
Haiyan Sun ◽  
Yi Ren
Keyword(s):  
Open Source ◽  
High Performance ◽  
Instruction Set ◽  
University Of Illinois ◽  
Specific Process ◽  
Defense Technology ◽  
Migration Mechanism ◽  
National University ◽  
Compiler Framework ◽  
The University

The processor FT_MX is a high-performance chip independently developed by the National University of Defense Technology, with an innovative architecture and instruction set. LLVM architecture is a widely used and efficient open source compiler framework initiated by the University of Illinois. This paper introduces the basic architecture and functions of LLVM, analyzes the back-end migration mechanism of the architecture in detail, and gives the specific process of implementing FT_MX back-end migration, and realizes the support of LLVM architecture to the back-end of FT_MX processor.

scholarly journals Two-Chains: High Performance Framework for Function Injection and Execution

2021 ◽  
Author(s):  
Megan Grodowitz ◽  
Luis E. Pena ◽  
Curtis Dunham ◽  
Dong Zhong ◽  
Pavel Shamis ◽  
...  
Keyword(s):  
High Performance ◽  
Performance Framework

scholarly journals Towards NeuroML: Model Description Methods for Collaborative Modelling in Neuroscience

2001 ◽  
Vol 356 (1412) ◽  
pp. 1209-1228 ◽  
Author(s):  
Nigel H. Goddard ◽  
Michael Hucka ◽  
Fred Howell ◽  
Hugo Cornelis ◽  
Kavita Shankar ◽  
...  
Keyword(s):  
High Performance ◽  
Computational Models ◽  
Object Oriented ◽  
Model Description ◽  
Specific Component ◽  
Nervous Systems ◽  
Efficient Simulation ◽  
Performance Framework ◽  
Structural Levels ◽  
Modelling Process

Biological nervous systems and the mechanisms underlying their operation exhibit astonishing complexity. Computational models of these systems have been correspondingly complex. As these models become ever more sophisticated, they become increasingly difficult to define, comprehend, manage and communicate. Consequently, for scientific understanding of biological nervous systems to progress, it is crucial for modellers to have software tools that support discussion, development and exchange of computational models. We describe methodologies that focus on these tasks, improving the ability of neuroscientists to engage in the modelling process. We report our findings on the requirements for these tools and discuss the use of declarative forms of model description—equivalent to object–oriented classes and database schema—which we call templates. We introduce NeuroML, a mark–up language for the neurosciences which is defined syntactically using templates, and its specific component intended as a common format for communication between modelling–related tools. Finally, we propose a template hierarchy for this modelling component of NeuroML, sufficient for describing models ranging in structural levels from neuron cell membranes to neural networks. These templates support both a framework for user–level interaction with models, and a high–performance framework for efficient simulation of the models.

DroidCollector: A High Performance Framework for High Quality Android Traffic Collection

2016 ◽  
Author(s):  
Dong Cao ◽  
Shanshan Wang ◽  
Qun Li ◽  
Zhenxiang Cheny ◽  
Qiben Yan ◽  
...  
Keyword(s):  
High Performance ◽  
High Quality ◽  
Performance Framework ◽  
Traffic Collection

scholarly journals A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set

2012 ◽  
Vol 2012 ◽  
pp. 1-10 ◽  
Author(s):  
Dau-Chyrh Chang ◽  
Lihong Zhang ◽  
Xiaoling Yang ◽  
Shao-Hsiang Yen ◽  
Wenhua Yu
Keyword(s):  
High Performance ◽  
Fdtd Method ◽  
Hardware Acceleration ◽  
Single Instruction Multiple Data ◽  
Instruction Set ◽  
Computer Cluster ◽  
Simulation Performance ◽  
Acceleration Technique ◽  
Multiple Data ◽  
Difference Time

We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set.

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