Concurrent Test Generation Using Concolic Multi-trace Analysis

Author(s):  
Niloofar Razavi ◽  
Franjo Ivančić ◽  
Vineet Kahlon ◽  
Aarti Gupta
2019 ◽  
Vol 15 (2) ◽  
pp. 143-151 ◽  
Author(s):  
Parviz Norouzi ◽  
Bagher Larijani ◽  
Taher Alizadeh ◽  
Eslam Pourbasheer ◽  
Mostafa Aghazadeh ◽  
...  

Background: The new progress in electronic devices has provided a great opportunity for advancing electrochemical instruments by which we can more easily solve many problems of interest for trace analysis of compounds, with a high degree of accuracy, precision, sensitivity, and selectivity. On the other hand, in recent years, there is a significant growth in the application of nanomaterials for the construction of nanosensors due to enhanced chemical and physical properties arising from discrete modified nanomaterial-based electrodes or microelectrodes. Objective: Combination of the advanced electrochemical system and nanosensors make these devices very suitable for the high-speed analysis, as motioning and portable devices. This review will discuss the recent developments and achievements that have been reported for trace measurement of drugs and toxic compounds for environment, food and health application.


Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.


2012 ◽  
Vol 42 (3) ◽  
pp. 257-271 ◽  
Author(s):  
Koffi Badjagbo ◽  
Sébastien Sauvé

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