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High-level modeling and exploration of a powerline communication network based on System-on-Chip
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures
◽
10.1007/978-1-4419-8837-9_7
◽
2011
◽
pp. 145-170
Author(s):
Marcos Martinez
◽
David Ferruz
◽
Hector Posadas
◽
Eugenio Villar
Keyword(s):
Communication Network
◽
System On Chip
◽
Powerline Communication
◽
High Level Modeling
◽
On Chip
◽
High Level
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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
10.1007/978-981-10-1073-6
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2018
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Zheng Wang
◽
Anupam Chattopadhyay
Keyword(s):
System On Chip
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High Level Estimation
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On Chip
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High Level System-on-Chip Design using UML and SystemC
Electronics, Robotics and Automotive Mechanics Conference (CERMA 2007)
◽
10.1109/cerma.2007.4367776
◽
2007
◽
Cited By ~ 1
Author(s):
Blanca Alicia Correa
◽
Juan Fernando Eusse
◽
Danny Munera
◽
Jose Edinson Aedo
◽
Juan Fernando Velez
Keyword(s):
System On Chip
◽
Level System
◽
Chip Design
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On Chip
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High Level
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Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI Technology
10.1109/norcas53631.2021.9599855
◽
2021
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Author(s):
Tobias Stuckenberg
◽
Malte Rucker
◽
Niklas Rother
◽
Rochus Nowosielski
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Frank Wiese
◽
...
Keyword(s):
Communication System
◽
System On Chip
◽
Harsh Environment
◽
Powerline Communication
◽
On Chip
◽
Soi Technology
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A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures
Journal of Low Power Electronics
◽
10.1166/jolpe.2009.1037
◽
2009
◽
Vol 5
(3)
◽
pp. 373-384
Author(s):
Sandro Penolazzi
◽
Ahmed Hemani
◽
Luca Bolognino
Keyword(s):
System On Chip
◽
Performance Estimation
◽
Level Energy
◽
And Performance
◽
On Chip
◽
High Level
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Multidimensional representation of ultrasonic data processed by Reconfigurable Ultrasonic System-on-Chip using OpenCL high-level synthesis
2014 IEEE International Ultrasonics Symposium
◽
10.1109/ultsym.2014.0481
◽
2014
◽
Cited By ~ 4
Author(s):
Spenser Gilliland
◽
Clementine Boulet
◽
Thomas Gonnot
◽
Jafar Saniie
Keyword(s):
System On Chip
◽
High Level Synthesis
◽
On Chip
◽
High Level
◽
Multidimensional Representation
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A Framework for High-Level Synthesis of System-on-Chip Designs
2005 IEEE International Conference on Microelectronic Systems Education (MSE'05)
◽
10.1109/mse.2005.8
◽
2006
◽
Cited By ~ 29
Author(s):
J.E. Stine
◽
J. Grad
◽
I. Castellanos
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J. Blank
◽
V. Dave
◽
...
Keyword(s):
System On Chip
◽
High Level Synthesis
◽
On Chip
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High Level
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Evaluation of Stencil Based Algorithm Parallelization over System-on-Chip FPGA Using a High Level Synthesis Tool
Communications in Computer and Information Science - Applied Computer Sciences in Engineering
◽
10.1007/978-3-030-31019-6_5
◽
2019
◽
pp. 52-63
Author(s):
Luis Castano-Londono
◽
Cristian Alzate Anzola
◽
David Marquez-Viloria
◽
Guillermo Gallo
◽
Gustavo Osorio
Keyword(s):
System On Chip
◽
High Level Synthesis
◽
Synthesis Tool
◽
On Chip
◽
High Level
◽
Algorithm Parallelization
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High-Level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2004.833612
◽
2004
◽
Vol 23
(9)
◽
pp. 1355-1361
◽
Cited By ~ 13
Author(s):
X. Bai
◽
S. Dey
Keyword(s):
System On Chip
◽
Simulation Methodology
◽
Defect Simulation
◽
On Chip
◽
High Level
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High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media
Journal of Systems Architecture
◽
10.1016/j.sysarc.2010.07.014
◽
2010
◽
Vol 56
(11)
◽
pp. 597-615
◽
Cited By ~ 1
Author(s):
Balal Ahmad
◽
Ali Ahmadinia
◽
Tughrul Arslan
Keyword(s):
Communication Media
◽
Automated Generation
◽
High Level Modeling
◽
On Chip
◽
High Level
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High-level system-on-chip simulator
2012 11th Conference of Open Innovations Association (FRUCT)
◽
10.23919/fruct.2012.8253117
◽
2012
◽
Cited By ~ 2
Author(s):
Aleksandr Orlov
◽
Alexey Syschikov
Keyword(s):
System On Chip
◽
Level System
◽
On Chip
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High Level
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