Balanced Wrapper Design to Test the Embedded Core Partitioned into Multiple Layer for 3D SOC Targeting Power and Number of TSVs
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2018 ◽
Vol 6
(4)
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pp. 236-241
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2016 ◽
Vol 55
(3)
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pp. 032101
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2004 ◽
Vol 19
(4-5)
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pp. 408-409
1987 ◽
Vol 227
(1-2)
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pp. 147-158
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