This paper scrutinises the present day setting practice for the high impedance type relay and the associated CT dimensioning. It is demonstrated that the present day practice for setting and CT dimensioning can cause delay in the relay operating time particularly if the CTs have residual flux in the direction of flux set up by the fault currents. The paper suggests methods to reduce the relay operation time and the fault clearance time by using the anti remanance CTs. Setting methodology for the anti-remanance CTs is also proposed. To overcome the delay in relay operation due to the poor transient response of the iron cored CTs, two new algorithms are proposed. These algorithms are simple and easily implementable in the numerical relays and can be used in systems where relay replacement is much easier than CT replacement. The concepts proposed in the paper are demonstrated by simulations using non linear mathematical models of CT and surge arrestors.
How Deviations in OPL Parameters Affect the Stability-Critical Fault Clearance Time