scholarly journals Design and Implementation of Advanced Encryption Standard Using Verilog HDL

2021 ◽  
pp. 483-498
Author(s):  
Shamsiah Binti Suhaili ◽  
Rene Brooke Fredrick ◽  
Zainah Md. Zain ◽  
Norhuzaimin Julai
Keyword(s):  
Advanced Encryption Standard ◽  
Verilog Hdl ◽  
Design And Implementation

Design and Implementation of USB Transceiver with Verilog

2013 ◽  
Vol 462-463 ◽  
pp. 604-608
Author(s):  
Li Kun Zheng ◽  
Ya Li Chen ◽  
Zhe Ying Li
Keyword(s):  
Verilog Hdl ◽  
Universal Serial Bus ◽  
Design And Implementation ◽  
Functional Blocks

The Universal Serial Bus Transceiver is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. In this paper, USB Transceiver is designed and implemented with Verilog HDL, This includes functions such as, data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit destuffing, deserialization. The transceiver is simulated by the modelsim software and the simulation wave is gave.

Design and Implementation of RAM Operation Conflict Arbiter IC in LED/LCD Display Control System

2012 ◽  
Vol 268-270 ◽  
pp. 1574-1577
Author(s):  
Zhao Jie ◽  
Fei Yu ◽  
Jing Xia Wang ◽  
Liu Li
Keyword(s):  
Control System ◽  
Low Cost ◽  
Structure Design ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
System A ◽  
Lcd Display ◽  
Working Principle ◽  
Fpga Chip ◽  
Display Control

To solve the writing and reading operation conflict to RAM in LED/LCD display control system, a new RAM operation conflict arbiter IC was proposed. Comparing the traditional dual ports RAM, the IC has the advantages of low-cost and high stability. By analyzing the working principle and structure design, the IC was designed in pure digital way with Verilog HDL, and passed the simulation verify. Finally the IC was realized by Alter FPGA chip and passed the actual test.

scholarly journals Design and Implementation of 8 point FFT using Verilog HDL

2019 ◽  
Vol 177 (11) ◽  
pp. 4-6
Author(s):  
Sonali Kangralkar ◽  
Rajashri Khanai
Keyword(s):  
Verilog Hdl ◽  
Design And Implementation

Design and Implementation of Floyd-Steinberg Algorithm Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 350-353
Author(s):  
Jun Yang ◽  
Zong Jing Li ◽  
Wen Long Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Complex Multiplication ◽  
Error Diffusion ◽  
Computation Complexity ◽  
Time Error ◽  
Verilog Hdl ◽  
Memory Space ◽  
Design And Implementation ◽  
Quartus Ii

In this paper, we put forward an innovation method of high-speed and real-time error diffusion, which is based on Floyd-Steinberg algorithm. The design introduces LUT(look up table) and pipeline technology instead of complex multiplication operations, which accesses to the memory frequently. The whole design uses Verilog HDL language to program and Quartus ii 8.0 to synthesize and layout. At the end of the paper, we use a 48 pixel as an example, then simulate and verify it on the Modesim, which can prove the correctness of the design. Compared with the standard Floyed-Steinberg algorithm, this design can reduce the computation complexity, use a smaller memory space to exchange lots of logic units and increase the throughput of the algorithm. Besides, it has the advantages of good reconfigurability, simple hardware structure and high real-time.

Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking

2015 ◽  
Vol 734 ◽  
pp. 621-624
Author(s):  
Qun Xiu Yu ◽  
Shou Ming Zhang ◽  
Chao Wang ◽  
Li Zhi Xie
Keyword(s):  
Integrated Circuits ◽  
Digital Watermarking ◽  
Image Watermarking ◽  
Simulation Software ◽  
Ip Core ◽  
Verilog Hdl ◽  
Jpeg Image ◽  
Design And Implementation ◽  
Watermark Embedding ◽  
Hardware Resource

In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.

scholarly journals Design and implementation of pipelined and parallel AES encryption systems using FPGA

2020 ◽  
Vol 20 (1) ◽  
pp. 287
Author(s):  
Mohamed Nabil ◽  
Ashraf A. M. Khalaf ◽  
Sara M. Hassan
Keyword(s):  
Big Data ◽  
Parallel Algorithms ◽  
Processing Time ◽  
Advanced Encryption Standard ◽  
Time Consumption ◽  
Design And Implementation ◽  
Aes Algorithm ◽  
Detailed Explanation ◽  
Encryption Algorithms ◽  
Parallel Techniques

<p><span>The information security is one of the most important issues in the design of any communication network.One of the most common encryption algorithms is the Advanced Encryption Standard (AES).The main problem facing the AES algorithm is the high time consumption due to the large number of rounds used for performing the encryption operation. The more time the encryption system consumes to encrypt the data, the more chances the hackers have to break the system.This paper presents two effective algorithms that can be used to solve the mentioned problem and to achieve an effective processing time reduction using pipelined and parallel techniques to perform the encryption steps. These algorithms are based on using certain techniques to make the system able to encrypt many different states (the data will be encrypted) in the same time with no necessity to wait for the previous encryption operation to be completed. These two algorithms are very effective especially for big data size. This paper describes in detail the AES encryption system algorithm and a detailed explanation for the proposed algorithms. Moreover, the research shows the implementation of the three algorithms: the traditional, the pipelined, and the parallel algorithms, and finally a comparison between them.</span></p>

Sign in / Sign up

Export Citation Format

Share Document