Design and Implementation of MD5 Hash Function Algorithm Using Verilog HDL

2021 ◽  
pp. 499-510
Author(s):  
Shamsiah Binti Suhaili ◽  
Cleopatra Chundang Anak Niam ◽  
Zainah Md. Zain ◽  
Norhuzaimin Julai
Keyword(s):  
Hash Function ◽  
Verilog Hdl ◽  
Design And Implementation

Design and Implementation of USB Transceiver with Verilog

2013 ◽  
Vol 462-463 ◽  
pp. 604-608
Author(s):  
Li Kun Zheng ◽  
Ya Li Chen ◽  
Zhe Ying Li
Keyword(s):  
Verilog Hdl ◽  
Universal Serial Bus ◽  
Design And Implementation ◽  
Functional Blocks

The Universal Serial Bus Transceiver is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. In this paper, USB Transceiver is designed and implemented with Verilog HDL, This includes functions such as, data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit destuffing, deserialization. The transceiver is simulated by the modelsim software and the simulation wave is gave.

Design and Implementation of RAM Operation Conflict Arbiter IC in LED/LCD Display Control System

2012 ◽  
Vol 268-270 ◽  
pp. 1574-1577
Author(s):  
Zhao Jie ◽  
Fei Yu ◽  
Jing Xia Wang ◽  
Liu Li
Keyword(s):  
Control System ◽  
Low Cost ◽  
Structure Design ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
System A ◽  
Lcd Display ◽  
Working Principle ◽  
Fpga Chip ◽  
Display Control

To solve the writing and reading operation conflict to RAM in LED/LCD display control system, a new RAM operation conflict arbiter IC was proposed. Comparing the traditional dual ports RAM, the IC has the advantages of low-cost and high stability. By analyzing the working principle and structure design, the IC was designed in pure digital way with Verilog HDL, and passed the simulation verify. Finally the IC was realized by Alter FPGA chip and passed the actual test.

scholarly journals Design and Implementation of 8 point FFT using Verilog HDL

2019 ◽  
Vol 177 (11) ◽  
pp. 4-6
Author(s):  
Sonali Kangralkar ◽  
Rajashri Khanai
Keyword(s):  
Verilog Hdl ◽  
Design And Implementation

Design and Implementation of Floyd-Steinberg Algorithm Based on FPGA

2015 ◽  
Vol 738-739 ◽  
pp. 350-353
Author(s):  
Jun Yang ◽  
Zong Jing Li ◽  
Wen Long Li
Keyword(s):  
Real Time ◽  
High Speed ◽  
Complex Multiplication ◽  
Error Diffusion ◽  
Computation Complexity ◽  
Time Error ◽  
Verilog Hdl ◽  
Memory Space ◽  
Design And Implementation ◽  
Quartus Ii

In this paper, we put forward an innovation method of high-speed and real-time error diffusion, which is based on Floyd-Steinberg algorithm. The design introduces LUT(look up table) and pipeline technology instead of complex multiplication operations, which accesses to the memory frequently. The whole design uses Verilog HDL language to program and Quartus ii 8.0 to synthesize and layout. At the end of the paper, we use a 48 pixel as an example, then simulate and verify it on the Modesim, which can prove the correctness of the design. Compared with the standard Floyed-Steinberg algorithm, this design can reduce the computation complexity, use a smaller memory space to exchange lots of logic units and increase the throughput of the algorithm. Besides, it has the advantages of good reconfigurability, simple hardware structure and high real-time.

Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking

2015 ◽  
Vol 734 ◽  
pp. 621-624
Author(s):  
Qun Xiu Yu ◽  
Shou Ming Zhang ◽  
Chao Wang ◽  
Li Zhi Xie
Keyword(s):  
Integrated Circuits ◽  
Digital Watermarking ◽  
Image Watermarking ◽  
Simulation Software ◽  
Ip Core ◽  
Verilog Hdl ◽  
Jpeg Image ◽  
Design And Implementation ◽  
Watermark Embedding ◽  
Hardware Resource

In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.

scholarly journals Design and Implementation of the Turbo Encoder by using Magnitude Comparator in IVS Chip

2021 ◽  
Vol 12 (6) ◽  
pp. 1537-1545
Author(s):  
Kesari Ananda Samhitha, Y. David Solomon Raju
Keyword(s):  
Parallel Computing ◽  
Low Power ◽  
Processing Time ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
Chip Size ◽  
Turbo Encoder ◽  
Variant System ◽  
Research Studies

This research studies the concept and application of the Turbo_encoder to be an integrated module in the In-Vehicle Device (IVS) embedded module by using the magnitude comparator. To create the Turbo_encoder Module, the complex PLDS are used. The variants of series and parallel Turbo_encoders are discussed. It is shown that proportional to chip size processing time also increased in the Turbo_encoder parallel computing variant system. The magnitude comparator with parallel computing variant system is implemented in this project. The usage of proposed logic resulted in efficient area and power usage. The architecture construction using Verilog HDL and implementation and simulation are executed in the Xilinx-ise tool. To incorporate the built module, Xilinx Vertex Low Power is used. The Turbo_encoder module on a single programmable computer is planned to be part of the IVS chip.

The Design and Implementation of Shortwave DFH Communication Receiver Based on FPGA

2012 ◽  
Vol 263-266 ◽  
pp. 1016-1020
Author(s):  
Nan Zhou ◽  
Xuan Zhao ◽  
Yong Xin Feng
Keyword(s):  
Communication System ◽  
Verilog Hdl ◽  
Design And Implementation ◽  
New Type

Shortwave DFH system is a new type of communication system, and it is widely used in various fields because of its good anti-interference and anti-fading ability performance in anti-interference and anti-fading. A shortwave DFH communication receiver is designed based on Virtex4-sx35 series FPGA development board using Verilog HDL and VHDL language, and the function of this receiver is implemented and simulated. The result of simulating shows that the designed shortwave DFH receiver is effectively.

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