Investigation of Analog Performance of In0.53Ga0.47As-Based Nanotube Double-Gate-All-Around (DGAA) MOSFET

Lecture Notes in Electrical Engineering - Recent Trends in Electronics and Communication ◽

10.1007/978-981-16-2761-3_8 ◽

2021 ◽

pp. 89-96

Author(s):

Nitish Kumar ◽

Himanshi Awasthi ◽

Vaibhav Purwar ◽

Abhinav Gupta ◽

Sanjeev Rai

Keyword(s):

Double Gate ◽

Analog Performance

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Impact of Source and Drain Underlap on Analog Performance of Double-Gate AlGaN/GaN MOS-HEMT

2020 IEEE Calcutta Conference (CALCON) ◽

10.1109/calcon49167.2020.9106543 ◽

2020 ◽

Author(s):

Shubham Kumar ◽

Minnat Ali ◽

Raushan Kumar ◽

Rajrup Mitra ◽

Atanu Kundu ◽

...

Keyword(s):

Double Gate ◽

Analog Performance

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Design and investigation of dopingless double-gate line tunneling transistor: Analog performance, linearity, and harmonic distortion analysis

Chinese Physics B ◽

10.1088/1674-1056/ab9c06 ◽

2020 ◽

Vol 29 (10) ◽

pp. 108502

Author(s):

Hui-Fang Xu ◽

Xin-Feng Han ◽

Wen Sun

Keyword(s):

Harmonic Distortion ◽

Double Gate ◽

Analog Performance ◽

Distortion Analysis

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Analog performance of the nanoscale double-gate metal-oxide-semiconductor field-effect-transistor near the ultimate scaling limits

Journal of Applied Physics ◽

10.1063/1.1778485 ◽

2004 ◽

Vol 96 (9) ◽

pp. 5271-5276 ◽

Cited By ~ 27

Author(s):

D. Jiménez ◽

B. Iñíguez ◽

J. Suñé ◽

J. J. Sáenz

Keyword(s):

Metal Oxide ◽

Field Effect ◽

Field Effect Transistor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Scaling Limits ◽

Double Gate ◽

Analog Performance ◽

Effect Transistor

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Impact of high-k dielectric on the digital and analog performance on emulation of double-gate UTBB SOI MOSFETs with different ground plane structures

2015 IEEE Regional Symposium on Micro and Nanoelectronics (RSM) ◽

10.1109/rsm.2015.7354984 ◽

2015 ◽

Author(s):

Noraini Othman ◽

M. K. Md Arshad ◽

S. N. Sabki ◽

U. Hashim

Keyword(s):

Ground Plane ◽

Double Gate ◽

High K ◽

Analog Performance ◽

High K Dielectric

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An Optimisation Based Study of Underlap Architecture of Sub 16 nm Double Gate MOSFET for Enhanced Analog Performance

Materials Focus ◽

10.1166/mat.2017.1402 ◽

2017 ◽

Vol 6 (3) ◽

pp. 305-309 ◽

Cited By ~ 3

Author(s):

Rahul Das ◽

Payel Pandit ◽

Shramana Chakraborty ◽

Arpan Dasgupta ◽

Atanu Kundu ◽

...

Keyword(s):

Double Gate ◽

Analog Performance ◽

Double Gate Mosfet

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Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

Semiconductor Science and Technology ◽

10.1088/1361-6641/abaaed ◽

2020 ◽

Vol 35 (10) ◽

pp. 105022

Author(s):

Vishal Narula ◽

Mohit Agarwal

Keyword(s):

Common Source ◽

Core Shell ◽

Double Gate ◽

Analog Performance ◽

Junctionless Transistor

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Analog performance of double gate junctionless tunnel field effect transistor

Journal of Semiconductors ◽

10.1088/1674-4926/35/7/074001 ◽

2014 ◽

Vol 35 (7) ◽

pp. 074001 ◽

Cited By ~ 6

Author(s):

M. W. Akram ◽

Bahniman Ghosh

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Double Gate ◽

Analog Performance ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

Journal of Semiconductors ◽

10.1088/1674-4926/36/9/094001 ◽

2015 ◽

Vol 36 (9) ◽

pp. 094001 ◽

Cited By ~ 2

Author(s):

S. Intekhab Amin ◽

R. K. Sarin

Keyword(s):

Double Gate ◽

Analog Performance ◽

Junctionless Transistor ◽

The Impact ◽

Dual Material

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Analog performance investigation of double gate junctionless transistor using spacer layer engineering

2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT) ◽

10.1109/icccnt.2017.8204086 ◽

2017 ◽

Author(s):

Nalineesh Chahal ◽

Gaurav Saini

Keyword(s):

Double Gate ◽

Analog Performance ◽

Spacer Layer ◽

Junctionless Transistor

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An Analysis of Analog Performance for High-K Gate Stack Dielectric Pocket Double-Gate-All-Around (DP-DGAA) MOSFET

Lecture Notes in Electrical Engineering - Recent Trends in Electronics and Communication ◽

10.1007/978-981-16-2761-3_6 ◽

2021 ◽

pp. 71-78

Author(s):

Vaibhav Purwar ◽

Rajeev Gupta ◽

Nitish Kumar ◽

Himanshi Awasthi ◽

Rakesh Kumar Pandey

Keyword(s):

Double Gate ◽

Gate Stack ◽

High K ◽

Analog Performance

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