Temperature Sensitivity Analysis of Dual Material Stack Gate Oxide Source Dielectric Pocket TFET

Temperature dependence performance variation is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, for the first time, the impact of temperature variations ranging from 300K to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel- field-effect transistor (DMSGO-SDP-TFET) is investigated. In this regard, technology computer-aided design (TCAD) simulator is used to analyze DC, and analog/radio frequency performance parameters such as carrier concentration, energy band variation, band to band tunneling rate, IDS - VGS characteristics, transconductance (gm), cut o frequency (f T ),gain-bandwidth product (GBP), maximum oscillating frequency (fmax), transconductance frequency product (TFP), and transit time considering the impact of temperature variations. Furthermore, linearity parameters such as third-order transconductance (gm3), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio frequency applications. Moreover, the performance of the proposed DMSGO- SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel- field-effect transistor (DMSGO-TFET). From the comparative analysis, in terms of % per kelvin, DMSGO-SDP-TFET demonstrates lesser sensitivity towards temperature variation. Hence, the proposed DMSGO-SDP-TFET can be a suitable candidate for low power switching and analog/radio frequency applications at elevated temperatures as compared to conventional DMSGO-TFET.

Characterization of silicon tunnel field effect transistor based on charge plasma

The aim of the proposed paper is an analytical model and realization of the characteristics for tunnel field-effect transistor (TFET) based on charge plasma (CP). One of the most applications of the TFET device which operates based on CP technique is the biosensor. CP-TFET is to be used as an effective device to detect the uncharged molecules of the bio-sample solution. Charge plasma is one of some techniques that recently invited to induce charge carriers inside the devices. In this proposed paper we use a high work function in the source (ϕ=5.93 eV) to induce hole charges and we use a lower work function in drain (ϕ=3.90 eV) to induce electron charges. Many electrical characterizations in this paper are considered to study the performance of this device like a current drain (ID) versus voltage gate (Vgs), ION/IOFF ratio, threshold voltage (VT) transconductance (gm), and sub-threshold swing (SS). The signification of this paper comes into view enhancement the performance of the device. Results show that high dielectric (K=12), oxide thickness (Tox=1 nm), channel length (Lch=42 nm), and higher work function for the gate (ϕ=4.5 eV) tend to best charge plasma silicon tunnel field-effect transistor characterization.

Investigation of DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

In this paper, a C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effect of pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I on ), on/off current ratio (I on /I off ), subthreshold swing (SS), transconductance (g m ), cut-off frequency (f T ), and gain-bandwidth product (GBP) are investigated. The optimized CSP-TFET device exhibits excellent performance with high I on (9.98×10-4 A/μm), high I on /I off (~1011), as well as low SS (~12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.