Operational transconductance amplifier-based comparator for high frequency applications using 22 nm FinFET technology

<p><span>Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.</span></p>

The impact of channel fin width on electrical characteristics of Si-FinFET

<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W_F=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

Top-gate field-effect transistor based on monolayer WS2 with an ion-gel gate dielectric

A top-gate field-effect transistor (FET), based on monolayer (ML) tungsten disulfide (WS2), and with an ion-gel dielectric was developed. The high electrical contact resistance of the Schottky contacts at the n-type transition metal dichalcogenides/metal electrode interfaces often adversely affects the device performance. We report the contact resistance and Schottky barrier height of an FET with Au electrodes. The FET is based on ML WS2 that was synthesised using chemical vapour deposition and was assessed using the transfer-length method and low-temperature measurements. Raman and photoluminescence spectra were recorded to determine the optical properties of the WS2 layers. The ML WS2 FET with an ion-gel top gate dielectric exhibits n-type behaviour, with a mobility, on/off ratio of 1.97 cm2/V·s, 1.51×105, respectively.

The influences of radiation effects on DC/RF performances of Lg=22 nm gate-all-around nanosheet field-effect transistor

In this paper, we carried out detailed TCAD simulations to investigate the radiation effects, e.g., total ionizing dose (TID) and single-event effects (SEEs), on direct current (DC) and radio frequency (RF) characteristics of the gate-all-around (GAA) nanosheet field-effect transistor (FET). The simulation model used is composed of 7-layer stacked GAA nanosheet FET with Lg=22 nm, which was implemented in this study. The open current and the drain-induced barrier lowering of the device are ~ 3mA/μm and 47mV/V, respectively. The results indicate that the TID have little influence on the DC and RF characteristics when the transistor is working in an open state. During the SEEs simulation, we considered three incident directions for the high energy particle, including the lateral direction of the channels, the vertical direction of the channels and the top of the channels. The influence of the particle injecting along the lateral and vertical directions of the channels shows stronger relation with the distance from the incident point compared to the influence of the particle from the top. Besides, the general influence of the particle injecting along the lateral directions of the channels is higher than the other two directions. The total injected charge of the particle injecting along the lateral direction, along the vertical direction and from the top are 3 fC, 1.4 fC and 2.1 fC, respectively. As compared to the FinFET, the GAA nanosheet has superior RF performances and less sensitivity to TID effect. This work can provide a guideline for the GAA nanosheet devices in aerospace and avionic RF applications.

Temperature Sensitivity Analysis of Dual Material Stack Gate Oxide Source Dielectric Pocket TFET

Temperature dependence performance variation is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, for the first time, the impact of temperature variations ranging from 300K to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel- field-effect transistor (DMSGO-SDP-TFET) is investigated. In this regard, technology computer-aided design (TCAD) simulator is used to analyze DC, and analog/radio frequency performance parameters such as carrier concentration, energy band variation, band to band tunneling rate, IDS - VGS characteristics, transconductance (gm), cut o frequency (f T ),gain-bandwidth product (GBP), maximum oscillating frequency (fmax), transconductance frequency product (TFP), and transit time considering the impact of temperature variations. Furthermore, linearity parameters such as third-order transconductance (gm3), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio frequency applications. Moreover, the performance of the proposed DMSGO- SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel- field-effect transistor (DMSGO-TFET). From the comparative analysis, in terms of % per kelvin, DMSGO-SDP-TFET demonstrates lesser sensitivity towards temperature variation. Hence, the proposed DMSGO-SDP-TFET can be a suitable candidate for low power switching and analog/radio frequency applications at elevated temperatures as compared to conventional DMSGO-TFET.