Affine Recurrence Based Key Scheduling Algorithm for the Advanced Encryption Standard

2021 ◽  
pp. 73-84
Author(s):  
S. Shashankh ◽  
Tavishi Kaushik ◽  
Svarnim Agarwal ◽  
C. R. Kavitha

RC6 (Rivest cipher 6) is keyblock chipher which consider symmetric imitative from RC5. It was intended to encounter the needs competition of the Advanced Encryption Standard (AES) . The aim of this work is to add new security layer to RC6 (Rivest Cipher 6) algorithm, because there is some insufficiency in the Key Scheduling Algorithm (KSA) of RC6. This paper presents improved RC6 (IRC6) key generation based on two types of chaotic maps (Chebyshev,2d logistic) to generate N key to N users. The results prove that the average secrecy of IRC6 is better than of traditional RC6, in which: for 32 bits’ key length, and 256 bits’ plaintext size, the average secrecy of IRC6 is (0.536 - 3.907) while for RC6 is (0.254 constant).


2018 ◽  
Vol 7 (2.14) ◽  
pp. 182
Author(s):  
Assia Merzoug ◽  
Adda Ali-Pacha ◽  
Naima Hadj-Said ◽  
Mustafa Mamat ◽  
Mohamad Afendee Mohamed

Cryptography came into picture as a tool to secure data in storage as well as under transmission. Stream cipher has been very famous for providing data confidentiality for vital communication such that found during the military operation. Various algorithms in existence, the two most important trade-off considered would be security and efficiency. The RC4 is a symmetric stream cipher which has been widely implemented in various applications such that of Mozilla and Microsoft. Recently, the algorithm is known for having a weak key schedule which gives rise to related key attacks and thus drove the algorithm to sideline. In this work, an attempt was made to propose an improved method based on the PWLCM map to generate a random sequence in key scheduling algorithm and to use it in the RC4. The novelty in this approach is the transformation of the RC4 algorithm, into a secret key encryption, with the increase of keyspace and thus improves the secu-rity of the key scheduling and in turn the RC4 algorithm. 


Author(s):  
Huda M. Salih ◽  
Raghda Salam Al Mahdawi

Digital technologies grow more rapidly; information security threats are becoming increasingly dangerous. Advanced and various cyber-attacks and security threats, like targeted emails, and information exploitation, pose a critical threat that basically undermines our trust in the digital society. Rivest cipher 4 (RC4) algorithm is a significant cipher of a stream that could be utilized with protocols of the internet, the advantage of the RC4 algorithm is that it is simple and effective. There are several weak, especially after the pseudo-random generation algorithm (PRGA), PRGA's initially 256 rounds (the amount of the RC4 permutation). Several modified RC4 studies have been published thus far, however, they all face either standard privacy or achievement evaluation issues. This paper proposes a new RC4 algorithm that is based on the user's retina (RC4-Retina), which has solved both of these weak points it was indicated in the standard RC4 algorithm. The novelty of retina key scheduling algorithm (RKSA), which is generated by relying on the user's retina of the algorithm will modify the matrix of permutation used to configure the keys. The efficiency of the improved algorithm was measured by depending on the average security of ciphertext of different keys and different messages, results were good compared to the standard algorithm.


Author(s):  
Somsak Choomchuay ◽  
Surapong Pongyupinpanich ◽  
Somsanouk Pathumvanh

This paper describes a compact 32-bit architecture developed for the Rijndael ciphering/deciphering system. The implementation is complied with NIST Advanced Encryption Standard (AES). The design processes any 128-bit block data with 128-bit key. For the compact hardware, the field inversion circuit and the key scheduling circuits are shared by both the encryption and decryption process. The on-the-fly KeyScheduling implementation offers fast processing speed but with core size trade-off. According to the evaluation made on the targeted FPGA, the design can offer the throughput of 768 mbps at 264 MHz clock speed.


Sign in / Sign up

Export Citation Format

Share Document