scholarly journals A Compact 32-bit Architecture for an AES System

Author(s):  
Somsak Choomchuay ◽  
Surapong Pongyupinpanich ◽  
Somsanouk Pathumvanh

This paper describes a compact 32-bit architecture developed for the Rijndael ciphering/deciphering system. The implementation is complied with NIST Advanced Encryption Standard (AES). The design processes any 128-bit block data with 128-bit key. For the compact hardware, the field inversion circuit and the key scheduling circuits are shared by both the encryption and decryption process. The on-the-fly KeyScheduling implementation offers fast processing speed but with core size trade-off. According to the evaluation made on the targeted FPGA, the design can offer the throughput of 768 mbps at 264 MHz clock speed.

Author(s):  
Krzysztof Bucholc ◽  
Krzysztof Chmiel ◽  
Anna Grocholewska-Czuryło ◽  
Ewa Idzikowska ◽  
Izabela Janicka-Lipska ◽  
...  

Scalable PP-1 block cipherA totally involutional, highly scalable PP-1 cipher is proposed, evaluated and discussed. Having very low memory requirements and using only simple and fast arithmetic operations, the cipher is aimed at platforms with limited resources, e.g., smartcards. At the core of the cipher's processing is a carefully designed S-box. The paper discusses in detail all aspects of PP-1 cipher design including S-box construction, permutation and round key scheduling. The quality of the PP-1 cipher is also evaluated with respect to linear cryptanalysis and other attacks. PP-1's concurrent error detection is also discussed. Some processing speed test results are given and compared with those of other ciphers.


Symmetry ◽  
2019 ◽  
Vol 11 (12) ◽  
pp. 1484 ◽  
Author(s):  
Oluwakemi Christiana Abikoye ◽  
Ahmad Dokoro Haruna ◽  
Abdullahi Abubakar ◽  
Noah Oluwatobi Akande ◽  
Emmanuel Oluwatobi Asani

The wide acceptability of Advanced Encryption Standard (AES) as the most efficient of all of the symmetric cryptographic techniques has further opened it up to more attacks. Efforts that were aimed at securing information while using AES is still being undermined by the activities of attackers This has further necessitated the need for researchers to come up with ways of enhancing the strength of AES. This article presents an enhanced AES algorithm that was achieved by modifying its SubBytes and ShiftRows transformations. The SubBytes transformation is modified to be round key dependent, while the ShiftRows transformation is randomized. The rationale behind the modification is to make the two transformations round key dependent, so that a single bit change in the key will produce a significant change in the cipher text. The conventional and modified AES algorithms are both implemented and evaluated in terms avalanche effect and execution time. The modified AES algorithm achieved an avalanche effect of 57.81% as compared to 50.78 recorded with the conventional AES. However, with 16, 32, 64, and 128 plain text bytes, the modified AES recorded an execution time of 0.18, 0.31, 0.46, and 0.59 ms, respectively. This is slightly higher than the results obtained with the conventional AES. Though a slightly higher execution time in milliseconds was recorded with the modified AES, the improved encryption and decryption strength via the avalanche effects measured is a desirable feat.


2011 ◽  
pp. 278-289
Author(s):  
Renato Saleri Lunazzi

The main goal of this chapter is to present a research project that consists of applying automatic generative methods in design processes. The initial approach briefly explores early theoretical conjectures, starting with form and function balance within former conceptual investigations. The following experiments describe original techniques introducing integrated 2-D and 3-D generators for the enhancement of recent 3-D Earth browsers (Virtual Terrain©, MSN Virtual Earth©, or Google Earth©) and cellularautomata processes for architectural programmatic optimization.


2019 ◽  
Vol 11 (8) ◽  
pp. 906 ◽  
Author(s):  
Zongyong Cui ◽  
Cui Tang ◽  
Zongjie Cao ◽  
Nengyuan Liu

Automatic target recognition (ATR) can obtain important information for target surveillance from Synthetic Aperture Radar (SAR) images. Thus, a direct automatic target recognition (D-ATR) method, based on a deep neural network (DNN), is proposed in this paper. To recognize targets in large-scene SAR images, the traditional methods of SAR ATR are comprised of four major steps: detection, discrimination, feature extraction, and classification. However, the recognition performance is sensitive to each step, as the processing result from each step will affect the following step. Meanwhile, these processes are independent, which means that there is still room for processing speed improvement. The proposed D-ATR method can integrate these steps as a whole system and directly recognize targets in large-scene SAR images, by encapsulating all of the computation in a single deep convolutional neural network (DCNN). Before the DCNN, a fast sliding method is proposed to partition the large image into sub-images, to avoid information loss when resizing the input images, and to avoid the target being divided into several parts. After the DCNN, non-maximum suppression between sub-images (NMSS) is performed on the results of the sub-images, to obtain an accurate result of the large-scene SAR image. Experiments on the MSTAR dataset and large-scene SAR images (with resolution 1478 × 1784) show that the proposed method can obtain a high accuracy and fast processing speed, and out-performs other methods, such as CFAR+SVM, Region-based CNN, and YOLOv2.


2013 ◽  
Vol 299 ◽  
pp. 172-175
Author(s):  
Wang Bin ◽  
Chong Ran Jiang ◽  
Jing Li

The paper designs a hard disk encryption system with pure software realization, the system uses the Windows driver development technology, uses the AES(Advanced Encryption Standard) algorithm as the hard disk encryption algorithm.It could protect sensitive information effectively without additional hardware devices and implements encryption and decryption for the whole hard disk.


2013 ◽  
Vol 712-715 ◽  
pp. 2733-2737
Author(s):  
Zhong An Yu ◽  
Chun Li Wang ◽  
Pei Yu Guo ◽  
Kong Kan

This system use PC as the core of image analysis and processing, with the single chip processor as the control core execution, combining with machine vision image processing technology, using advanced image processing algorithms, to achieve separation of the nut, and through experiments to test the correctness of the algorithm. The system has the advantage of a fast processing speed and high reliability. It not only save the manpower cost, but also improve the efficiency of the nut sorting.


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