Reconfigurable Architectures with High-Frequency Noise Suppression for Wearable ECG Devices

Recent advances in electronics and microelectronics have aided the development of low-cost devices that are widely used as well-being or preventive monitoring devices by many people. Remote health monitoring, which includes wearable sensors, actuators, and modern communication and information systems, offers effective programs that allow people to live peacefully in their own homes while also being protected in some way. High-frequency noise, power-line interface, and baseline drift are prevalent during the data-acquisition system of an ECG signal, and they can limit signal understanding. They (noises) must be isolated in order to provide an appropriate diagnostic of the patient. When removing high-frequency components (noise) from an ECG signal with an FIR filter, the critical path delay increases considerably as the filter's duration increases. To reduce high-frequency noise, simple moving average filters with pipelining and look-ahead transformation techniques are extensively used in this study. With the use of pipelining and look-ahead techniques, the only objective is to increase the clock speed of the designs. The moving average filters (conventional and proposed) were created on an Altera Cyclone IV FPGA EP4CE115F29C7 chip using the Quartus II software v13.1 tool. Finally, performance metrics such logic elements, clock speed, and power consumption were compared and studied thoroughly. The recursive pipelined 8-tap MA filter with look-ahead approach outperforms the other designs (685.48 MHz) in this investigation.

Examining the effect of Libet clock stimulus parameters on temporal binding

Temporal binding refers to the subjective temporal compression between actions and their outcomes. It is widely used as an implicit measure of sense of agency, that is, the experience of controlling our actions and their consequences. One of the most common measures of temporal binding is the paradigm developed by Haggard, Clark and Kalogeras (2002) based on the Libet clock stimulus. Although widely used, it is not clear how sensitive the temporal binding effect is to the parameters of the clock stimulus. Here, we present five experiments examining the effects of clock speed, number of clock markings and length of the clock hand on binding. Our results show that the magnitude of temporal binding increases with faster clock speeds, whereas clock markings and clock hand length do not significantly influence temporal binding. We discuss the implications of these results.

A hardware based technique to reduce the timing complexity of number factoring problem

Most digital circuits which have been developed to implement algorithms, can benefit from an increase in clock speed, but do not completely map the problem to all available silicon resources. We have introduced a hardware based scheme capable of effectively using technology, specifically the increase in silicon area, to improve the computational time of complicated applications. In this thesis, we applied this scheme to solve the factoring problem, which requires exponential time (with respect to the number of bits in n) in conventional computers and could be only solved in polynomial time with quantum computers. The scheme successfully mapped the problem to most of the silicon area of Altera Stratix FPGA. The results show that the scheme is capable of reducing the time complexity to a polynomial rate with respect to the number of bits of the number n. The results also show an exponential rate of use for silicon with respect to the number of bits of n. Our analysis shows that the new scheme is scalable with technology speed and available space, could be applied to other applications to solve the performance limitations of conventional systems.

A hardware based technique to reduce the timing complexity of number factoring problem

Most digital circuits which have been developed to implement algorithms, can benefit from an increase in clock speed, but do not completely map the problem to all available silicon resources. We have introduced a hardware based scheme capable of effectively using technology, specifically the increase in silicon area, to improve the computational time of complicated applications. In this thesis, we applied this scheme to solve the factoring problem, which requires exponential time (with respect to the number of bits in n) in conventional computers and could be only solved in polynomial time with quantum computers. The scheme successfully mapped the problem to most of the silicon area of Altera Stratix FPGA. The results show that the scheme is capable of reducing the time complexity to a polynomial rate with respect to the number of bits of the number n. The results also show an exponential rate of use for silicon with respect to the number of bits of n. Our analysis shows that the new scheme is scalable with technology speed and available space, could be applied to other applications to solve the performance limitations of conventional systems.

Quantifying thermal transport in buried semiconductor nanostructures via Cross-Sectional Scanning Thermal Microscopy

Managing thermal transport in nanostructures became a major challenge in development of active microelectronic, optoelectronic and thermoelectric devices, stalling the famous Moore’s law of clock speed increase of microprocessors for...

The effect of an unexpected modality on time reproduction: Clock speed or memory mixing?

The pacemaker-counter model (PCM) has been the core architecture of scalar expectancy theory for decades. PCM assumes the same timing mechanism applies to every stimulus input, regardless of modality, and has been used to explain differences between perceived durations. In violation, previous studies demonstrate a robust effect of memory-mixing, occurring when the memory trace of a previous time interval influences perception of upcoming ones. We examined the influence of unexpected modality for a trained duration on temporal reproduction, using auditory/visual stimuli with short/long (500/1000ms) standard durations—testing the PCM pure ‘clock speed’ prediction against the memory-mixing account. Here, we report different outcomes of unexpected modality on time reproduction based on modality assignments with specific intervals. When the short interval was trained with an auditory stimulus, and long interval with a visual stimulus, unexpected presence of the opposite modality led to a memory-mixing pattern, in which reproductions shifted toward the other interval. However, no such effect occurred when the short interval was trained with a visual stimulus and long interval with an auditory stimulus. We propose that durations stored in reference memory retain its paired modality, but that during averaging durations are combined based on both their modality and relative duration.

Competitive Cycles in a Hyper-Connected World

This chapter presents a competitive framework suggesting a circular perspective in analyzing and managing competitive wars in a hyper-competitive and hyper-connected world. The author uses the expression “competitive cycles” to represent a typical journey of a competitive arena. The journey starts with the status quo, characterized by a direct confrontation on specific success factors (War of Position); eventually, this scenario is disrupted by the game-changing strategy of an insurgent (War of Movement). This leads to the next stage of the journey, the War of Imitation, ending up when the new game finally becomes the new status quo, that is, back to the War of Position. Then everything flows, until a new cycle, with its new rules, will start again. The digital tsunami is adding momentum and clock-speed to competitive cycles. In every moment of a firm's life, then, it is vitally important to be fully aware of its different wars. In fact, behind each of them lies distinctive rationales and dynamics, which call for specific strategic approaches.