Concurrent Architecture-Based Fast Fourier Transform on FPGA IP Cores

Author(s):  
Varun Maheshwari ◽  
Mahendra Singh ◽  
Pooja Pandit ◽  
Reshu Aggarwal ◽  
Arun Navputra ◽  
...  

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Anatolij Sergiyenko ◽  
Anastasia Serhienko

A set of soft IP cores for the Winogradr-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm byrtimes. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.



1974 ◽  
Author(s):  
D. PHELPS ◽  
J. BAUMGARDNER ◽  
G. CANAVAN


1999 ◽  
Vol 2 (4) ◽  
pp. 61-73 ◽  
Author(s):  
Peter Carr ◽  
Dilip Madan




2010 ◽  
Author(s):  
Kwai Sun Leung ◽  
Hoi Ying Wong ◽  
Yue Kuen Kwok


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