Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

A High-Precision and Wideband Fundamental Frequency Measurement Method for Synchronous Sampling Used in the Power Analyzer

In the dedicated high-precision power quality analyzer, synchronous sampling is required to reduce the effect of spectrum leakage produced by the discrete Fourier transform process. Thus, accurate fundamental frequency measurement is urgently needed. However, due to the harmonics and noise in the power signal, it is difficult to achieve the accurate fundamental frequency measurement. Moreover, with the wide application of high-frequency programmable power supply, the fundamental frequency is gradually increasing, which requires power analyzers to have the abilities of both high precision and a wide range of the fundamental frequency measurement. To solve these issues, a new fundamental frequency measurement architecture used in synchronous sampling is proposed. This architecture consists of a small-point fast Fourier transform module, spectrum refinement algorithm, and a multimodal optimization method to calculate the accurate fundamental frequency under large harmonic conditions. In the practical hardware platform results, this architecture has a large fundamental frequency measurement range from 20 Hz to 200 kHz with a relative error which is <0.004%. The wideband fundamental frequency measurement structure proposed in this article achieves high measurement accuracy.

Implementation of a fully implantable middle-ear hearing device chip

BACKGROUND AND OBJECTIVE: Recently, with the increase in the population of hearing impaired people, various types of hearing aids have been rapidly developed. In particular, a fully implantable middle ear hearing device (F-IMEHD) is developed for people with sensorineural hearing loss. The F-IMEHD system comprises an implantable microphone, a transducer, and a signal processor. The signal processor should have a small size and consume less power for implantation in a human body. METHODS: In this study, we designed and fabricated a signal-processing chip using the modified FFT algorithm. This algorithm was developed focusing on eliminating time delay and system complexity in the transform process. The designed signal-processing chip comprises a 4-channel WDRC, a fitting memory, a communication 1control part, and a pulse density modulator. Each channel is separated using a 64-point fast Fourier transform (FFT) method and the gain value is matched using the fitting table in the fitting memory. RESULTS AND CONCLUSION: The chip was designed by Verilog-HDL and the designed HDL codes were verified by Modelsim-PE 10.3 (Mentor graphics, USA). The chip was fabricated using a 0.18 μm CMOS process (SMIC, China). Experiments were performed on a cadaver to verify the performance of the fabricated chip.

Empirical Characterization of the Temporal Dynamics of EEG Spectral Components

The properties of time-domain electroencephalographic data have been studied extensively. There has however been no attempt to characterize the temporal evolution of resulting spectral components when successive segments of electroencephalographic data are decomposed. We analysed resting-state scalp electroencephalographic data from 23 subjects, acquired at 256 Hz, and transformed using 64-point Fast Fourier Transform with a Hamming window. KPSS and Nason tests were administered to study the trend- and wide sense stationarity respectively of the spectral components. Their complexities were estimated using fuzzy entropy. Thereafter, the rosenstein algorithm for dynamic evolution was applied to determine the largest Lyapunov exponents of each component’s temporal evolution. We found that the evolutions were wide sense stationary for time scales up to 8 s, and had significant interactions, especially between spectral series in the frequency ranges 0-4 Hz, 12-24 Hz, and 32-128 Hz. The highest complexity was in the 12-24 Hz band, and increased monotonically with scale for all band sizes. However, the complexity in higher frequency bands changed more rapidly. The spectral series were generally non-chaotic, with average largest Lyapunov exponent of 0. The results show that significant information is contained in all frequency bands, and that the interactions between bands are complicated and time-varying.

Dynamic Frequency Scaling of a Single-Core Processor Using Machine Learning Paradigms

Dynamic frequency scaling (DFS) is one of the most important approaches for on-the-fly power optimization in modern-day processors. Owing to the trend of chip size shrinkage and increasing the complexity of system design, the problem of achieving an efficient DFS depends upon multi-parametric, non-linear optimization. Hence, it becomes extremely important to identify an optimal underclocking frequency on-the-fly, which depends upon numerous parameters that do not share direct relationship amongst each other. This paper proposes a machine learning approach to DFS of a ubiquitous single-core processor. Several performance parameters of the processor were monitored under an application of a number of clocking frequencies. The dataset thus generated was used to train four artificial neural networks (ANNs) viz. generalized regression (GRNN), decision tree classifier, random forest classifier and backpropagation technique. Under changing parametric conditions of the proposed network, the modes were fit to data while running three applications, i.e. 64- and 1024-point fast fourier transform (FFT) and basicmath applications. The performance of all ANNs was found to be promising and good generalization was obtained with all datasets. In the view of optimizing both speed and power of a system, the results indicate towards suitability of trained GRNN for on-chip deployment for implementing DFS.

Programmable FFT Processor using Dual RAM and ROM Technologies for Future 5G Communications

The high-throughput programmable Fast Fourier transform processor supports the usage of 2-stream 1024/2048/4096-point Fast Fourier Transforms and 1-to 4- stream 64/128-point Fast Fourier Transform for 4G,wireless local networks and for 5G.The proposed architecture which was designed is a well-intentionedfour-bank single-port SRAM which is being working in four-word data width, the design which is proposed gives us sixteen memory pathways . where the data is accessed up to this extent where it can be used in upcoming 5G. The radix-16 butterfly process element comprises of 2 cascaded parallel, pipelined radix-4 butterfly units which is specified. The projected memory-addressing methodology will effectively wear down single-port, merged-bank memory with high-radix process components. Comparing with typical memory based Fast Fourier Transform styles, the derived design has higher performance in expressions of area and power consumption. The architecture which is projected occupies the tiniest area of around1.21mm2 .The processor supports 1966MS/s 4096-point FFT and frequency of 1GHz.The Electronic design automation synthesis results show the power consumption is 32.16mW.The SQNR performance analysis is 42.14 dB.

Double Precision Floating Point Fft Processor using Vedic Mathematics

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

Implementation of 1024-point FFT Soft-Core to Characterize Power and Resource Parameters in Artix-7, Kintex-7, Virtex-7, and Zynq-7000 FPGAs

This Paper presents implementation of 1024-point Fast Fourier Transform (FFT). The MatLab simulink environment approach is used to implement the complex 1024-point FFT. The FFT is implemented on different FPGAs such as the following four: Artix-7, Kintex-7, Virtex-7, and Zynq-7000. The comparative study on power and resource consumption has been carried out as design parameters of prime concern. The results show that Artix-7 FPGA consumes less power of 3.402W when compared with its contemporary devices, mentioned above. The resource consumption remains same across all the devices. The resource estimation on each FPGA is carried on and its results are presented for 1024-point FFT function implementation. This Comprehensive analysis provides a deep insight with respect to power and resources. The synthesis and implementation results such as RTL Schematic, I/O Planning, and Floor Planning are generated and analyzed for all the above devices.

Combustion Instabilities of Separated Stratified Swirling Flames With Different Degrees of Premixedness

The effects of premixedness degrees on combustion instabilities of separated stratified swirling flames have been investigated experimentally in the Beihang Axial Swirler Independently-Stratified (BASIS) burner. The degree of premixedness is modulated by the fuel split between two injection positions in the outer stream. In the spectra of pressure oscillations, both the dominant frequency and amplitude of partially premixed flames are positively correlated with fuel split ratios. The partially premixed flame is found to feature a large-scale periodic convective motion based on CH* chemiluminescence images, which have been analyzed under different fuel split ratios by a point-to-point Fast Fourier Transform (FFT) method. The development of above convective motion is explained by combining the variation of pressure and heat release in the oscillation period. Local Rayleigh index maps show that the driving factor of combustion instability for the partially premixed flame mainly comes from the upstream of the combustor. Finally, thermoacoustic network analysis is applied to predict observed frequencies under both perfectly and partially premixed conditions. The supposed additional convective time due to equivalence ratio fluctuations and the elongated flame region for the partially premixed flame is validated by its longer time delay in the sensitivity analysis of the n-τ flame model.