scholarly journals Modules for Pipelined Mixed Radix FFT Processors

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Anatolij Sergiyenko ◽  
Anastasia Serhienko
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
High Speed ◽  
Sampling Frequency ◽  
Data Sampling ◽  
Clock Frequency ◽  
Ip Cores ◽  
Point Fast Fourier Transform ◽  
The Cost

A set of soft IP cores for the Winogradr-point fast Fourier transform (FFT) is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm byrtimes. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.

scholarly journals Programmable FFT Processor using Dual RAM and ROM Technologies for Future 5G Communications

2020 ◽  
Vol 9 (6) ◽  
pp. 1116-1122
Keyword(s):  
Fourier Transform ◽  
Power Consumption ◽  
Fast Fourier Transform ◽  
Fourier Transforms ◽  
Single Port ◽  
Local Networks ◽  
Parallel Pipelined ◽  
4G Wireless ◽  
Derived Design ◽  
Point Fast Fourier Transform

The high-throughput programmable Fast Fourier transform processor supports the usage of 2-stream 1024/2048/4096-point Fast Fourier Transforms and 1-to 4- stream 64/128-point Fast Fourier Transform for 4G,wireless local networks and for 5G.The proposed architecture which was designed is a well-intentionedfour-bank single-port SRAM which is being working in four-word data width, the design which is proposed gives us sixteen memory pathways . where the data is accessed up to this extent where it can be used in upcoming 5G. The radix-16 butterfly process element comprises of 2 cascaded parallel, pipelined radix-4 butterfly units which is specified. The projected memory-addressing methodology will effectively wear down single-port, merged-bank memory with high-radix process components. Comparing with typical memory based Fast Fourier Transform styles, the derived design has higher performance in expressions of area and power consumption. The architecture which is projected occupies the tiniest area of around1.21mm2 .The processor supports 1966MS/s 4096-point FFT and frequency of 1GHz.The Electronic design automation synthesis results show the power consumption is 32.16mW.The SQNR performance analysis is 42.14 dB.

scholarly journals Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

2021 ◽  
Vol 16 (2) ◽  
pp. 1-11
Author(s):  
André Sapper ◽  
Guilherme Paim ◽  
Eduardo Antônio César Da Costa ◽  
Sergio Bampi
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Power Efficiency ◽  
Cordic Algorithm ◽  
Standard Cell ◽  
Clock Gating ◽  
Power Efficient ◽  
Coordinate Rotation ◽  
Hardware Architectures ◽  
Point Fast Fourier Transform

This work explores hardware-oriented optimizations for the CORDIC (COordinate Rotation Digital Computer) algorithm investigating the power-efficiency improvements employing N-point Fast Fourier Transform (FFT) hardware architectures. We introduced three hardware-oriented optimizations for the CORDIC: (a) improving the signal extension, (b) removing the angle accumulation and (c) eliminating the redundancies in the iterations, both unnecessary when processing the FFT processing. Fully sequential FFT architectures of 32, 64, 128, and 256 points were synthesized employing ST 65 nm standard cell libraries. The results show up to 38% of power savings on average when using our best CORDIC optimization proposal to the FFT architecture comparing to the explicit multiply-based butterfly version. Moreover, when combining our best CORDIC optimization with the clock-gating technique, the power savings rises to 78.5% on average for N-point FFT.

scholarly journals Series Arc Fault Breaker in Low Voltage Using Microcontroller Based on Fast Fourier Transform

2021 ◽  
Vol 9 (2) ◽  
pp. 239-251
Author(s):  
Dimas Okky Anggriawan ◽  
Audya Elisa Rheinanda ◽  
Muhammad Khanif Khafidli ◽  
Eka Prasetyono ◽  
Novie Ayub Windarko
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Real Time ◽  
High Speed ◽  
Low Voltage ◽  
Resistive Load ◽  
Gas Ionization ◽  
Primary Driver ◽  
Experimental Process ◽  
Ac Arc

Series Arc Fault is one of the disturbances of arcing jump is caused by gas ionization between two ends of damaged conductors or broken wire forming a gap in the insulator. Series arc fault is the primary driver of electrical fire. However, lack of knowledge of the disturbance of series arc fault causes the problem of electrical fire not be mitigated. Magnitude current is not capable to detect of series arc fault. Therefore, this paper proposes fast fourier transform (FFT) to detect series AC arc fault in low voltage using microcontroller ARM STM32F7NGH in real time. A cheap and high speed of microcontroller ARM STM32F7NGH can be used for FFT computation to transform signal in time domain to frequency domain. Moreover, in this paper, protection of series AC arc fault is proposed in the real time mode. In this experimental process, some various experiments are tested to evaluate the reliability of FFT and protection with various load starts from 1 A, 2 A, 3 A, 4 A in resistive load. The result of this experiment shows that series AC arc fault protection with STM32F7 microcontroller and FFT algorithm can be utilized to ensure series AC arc fault properly.

scholarly journals Reducing the Cost of Implementing Filters in LoRa Devices

Sensors ◽  
2019 ◽  
Vol 19 (18) ◽  
pp. 4037
Author(s):  
Shania Stewart ◽  
Ha H. Nguyen ◽  
Robert Barton ◽  
Jerome Henry
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
System Performance ◽  
Pulse Shaping ◽  
Error Rates ◽  
Lookup Table ◽  
Significant Performance ◽  
High Level ◽  
The Cost ◽  
The Impact

This paper presents two methods to optimize LoRa (Low-Power Long-Range) devices so that implementing multiplier-less pulse shaping filters is more economical. Basic chirp waveforms can be generated more efficiently using the method of chirp segmentation so that only a quarter of the samples needs to be stored in the ROM. Quantization can also be applied to the basic chirp samples in order to reduce the number of unique input values to the filter, which in turn reduces the size of the lookup table for multiplier-less filter implementation. Various tests were performed on a simulated LoRa system in order to evaluate the impact of the quantization error on the system performance. By examining the occupied bandwidth, fast Fourier transform used for symbol demodulation, and bit-error rates, it is shown that even performing a high level of quantization does not cause significant performance degradation. Therefore, the memory requirements of LoRa devices can be significantly reduced by using the methods of chirp segmentation and quantization so as to improve the feasibility of implementing multiplier-less filters in LoRa devices.

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