Pseudo-random test generation for large combinational circuits

Journal of Computer Science and Technology ◽

10.1007/bf02946162 ◽

1992 ◽

Vol 7 (1) ◽

pp. 19-28 ◽

Author(s):

Zhongcheng Li ◽

Yinghua Min

Keyword(s):

Test Generation ◽

Combinational Circuits ◽

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Merit based directed random test generation (MDRTG) scheme for combinational circuits

2010 East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2010.5742157 ◽

2010 ◽

Author(s):

Arezoo Kamran ◽

Mohammad Saeed Jahangiry ◽

Zainalabedin Navabi

Keyword(s):

Test Generation ◽

Combinational Circuits ◽

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SCOAP-based Directed Random Test Generation for Combinational Circuits

2019 IEEE East-West Design & Test Symposium (EWDTS) ◽

10.1109/ewdts.2019.8884405 ◽

2019 ◽

Author(s):

Seyyede Maryam Ghasemy ◽

Maryam Rajabalipanah ◽

Saeideh Sarmadi ◽

Zainalabedin Navabi

Keyword(s):

Test Generation ◽

Combinational Circuits ◽

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Hierarchical test generation for combinational circuits with real defects coverage

Microelectronics Reliability ◽

10.1016/s0026-2714(02)00080-x ◽

2002 ◽

Vol 42 (7) ◽

pp. 1141-1149 ◽

Author(s):

T Cibáková ◽

M Fischerová ◽

E Gramatová ◽

W Kuzmicz ◽

W.A Pleskacz ◽

...

Keyword(s):

Test Generation ◽

Combinational Circuits

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NEST: a nonenumerative test generation method for path delay faults in combinational circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.476581 ◽

1995 ◽

Vol 14 (12) ◽

pp. 1505-1515 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy ◽

P. Uppaluri

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults

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A cone-based genetic optimization procedure for test generation and its application to n-detections in combinational circuits

IEEE Transactions on Computers ◽

10.1109/12.805164 ◽

1999 ◽

Vol 48 (10) ◽

pp. 1145-1152 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Optimization Procedure ◽

Genetic Optimization ◽

Combinational Circuits

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Test generation for redundant faults in combinational circuits by using delay effects

Proceedings of IEEE 3rd Asian Test Symposium (ATS) ◽

10.1109/ats.1994.367245 ◽

2002 ◽

Author(s):

X. Yu ◽

H. Takahashi ◽

Y. Takamatsu

Keyword(s):

Test Generation ◽

Combinational Circuits ◽

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3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set

The Fifth International Conference on VLSI Design ◽

10.1109/icvd.1992.658037 ◽

2005 ◽

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

Test Set ◽

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Research and implementation of a high speed test generation for ultra large scale combinational circuits

Proceedings Eighth Asian Test Symposium (ATS'99) ◽

10.1109/ats.1999.810731 ◽

2003 ◽

Author(s):

Zhide Zeng ◽

Jihua Chen ◽

Hefeng Cao

Keyword(s):

Test Generation ◽

Large Scale ◽

Combinational Circuits ◽

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An efficient automatic test generation system for path delay faults in combinational circuits

Proceedings of the 8th International Conference on VLSI Design ◽

10.1109/icvd.1995.512097 ◽

2002 ◽

Author(s):

A.K. Majhi ◽

J. Jacob ◽

L.M. Patnaik ◽

V.D. Agrawal

Keyword(s):

Test Generation ◽

Delay Faults ◽

Combinational Circuits ◽

Path Delay Faults ◽

Generation System ◽

Automatic Test Generation ◽

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An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits

Proceedings of the Fourth Asian Test Symposium ◽

10.1109/ats.1995.485342 ◽

2002 ◽

Author(s):

D.R. Chakrabarti ◽

A. Jain

Keyword(s):

Test Generation ◽

Combinational Circuits ◽

Generation Technique

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