CMOS designs have some unique properties that prevent existing test generators from
computing a test vector for a fault when one might exist. The problem lies in the
premises laid out on what it takes to detect a stuck-at fault. The basic premise that states
that it is required to set a line to 0(1) in order to detect a stuck-at 1(0) fault, and then
propagate the error to an observable point, needs to be re-examined. This is due to the
existence of indeterminate states throughout the logic. The paper distinguishes between
the traditional test vector (here called a hard-detect), and a potential test vector (here
called a soft-detect). Our proposed test set is the union of hard and soft-detects. We also
re-examine the issue of redundancy and show that it needs to be re-defined in order to
comply with CMOS technology behavior.This paper shows several examples to illustrate the problem; describes what it takes in
order to remedy it; proposes possible enhancements to existing test generation
algorithms, and outlines the risks faced in the event that no correcting steps are taken.
Test Generators Need to be Modified to Handle CMOS Designs