Measuring Fault Tolerance with the FTAPE fault injection tool

ARINC653 Channel Robustness Verification Using LeonViP-MC, a LEON4 Multicore Virtual Platform

Electronics ◽

10.3390/electronics10101179 ◽

2021 ◽

Vol 10 (10) ◽

pp. 1179

Author(s):

Jonatan Sánchez ◽

Antonio da Silva ◽

Pablo Parra ◽

Óscar R. Polo ◽

Agustín Martínez Hellín ◽

...

Keyword(s):

Fault Tolerance ◽

Architectural Design ◽

Fault Injection ◽

Control Unit ◽

Tolerance Mechanisms ◽

Efficient Data ◽

Instrument Control ◽

Virtual Platform ◽

Hardware Platforms ◽

The University

Multicore hardware platforms are being incorporated into spacecraft on-board systems to achieve faster and more efficient data processing. However, such systems lead to increased complexity in software development and represent a considerable challenge, especially concerning the runtime verification of fault-tolerance requirements. To address the ever-challenging verification of this kind of requirement, we introduce a LEON4 multicore virtual platform called LeonViP-MC. LeonViP-MC is an evolution of a previous development called Leon2ViP, carried out by the Space Research Group of the University of Alcalá (SRG-UAH), which has been successfully used in the development and testing of the flight software of the instrument control unit (ICU) of the energetic particle detector (EPD) on board the Solar Orbiter. This paper describes the LeonViP-MC architectural design decisions oriented towards fault-injection campaigns to verify software fault-tolerance mechanisms. To validate the simulator, we developed an ARINC653 communications channel that incorporates fault-tolerance mechanisms and is currently being used to develop a hypervisor level for the GR740 platform.

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A Method to Support Fault Tolerance Design in Service Oriented Computing Systems

Theoretical and Analytical Service-Focused Systems Design and Development ◽

10.4018/978-1-4666-1767-4.ch019 ◽

2012 ◽

pp. 362-376

Author(s):

Domenico Cotroneo ◽

Antonio Pecchia ◽

Roberto Pietrantuono ◽

Stefano Russo

Keyword(s):

Fault Tolerance ◽

Common Ground ◽

Fault Injection ◽

Failure Behavior ◽

Tolerance Design ◽

System Failure ◽

Computing Systems ◽

Service Oriented Computing ◽

Service Oriented ◽

Tailored Design

Service Oriented Computing relies on the integration of heterogeneous software technologies and infrastructures that provide developers with a common ground for composing services and producing applications flexibly. However, this approach eases software development but makes dependability a big challenge. Integrating such diverse software items raise issues that traditional testing is not able to exhaustively cope with. In this context, tolerating faults, rather than attempt to detect them solely by testing, is a more suitable solution. This paper proposes a method to support a tailored design of fault tolerance actions for the system being developed. This paper describes system failure behavior through an extensive fault injection campaign to figure out its criticalities and adopt the most appropriate countermeasures to tolerate operational faults. The proposed method is applied to two distinct SOC-enabling technologies. Results show how the achieved findings allow designers to understand the system failure behavior and plan fault tolerance.

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A Method to Support Fault Tolerance Design in Service Oriented Computing Systems

International Journal of Systems and Service-Oriented Engineering ◽

10.4018/jssoe.2010070105 ◽

2010 ◽

Vol 1 (3) ◽

pp. 75-89

Author(s):

Domenico Cotroneo ◽

Antonio Pecchia ◽

Roberto Pietrantuono ◽

Stefano Russo

Keyword(s):

Fault Tolerance ◽

Common Ground ◽

Fault Injection ◽

Failure Behavior ◽

Tolerance Design ◽

System Failure ◽

Computing Systems ◽

Service Oriented Computing ◽

Service Oriented ◽

Tailored Design

Service Oriented Computing relies on the integration of heterogeneous software technologies and infrastructures that provide developers with a common ground for composing services and producing applications flexibly. However, this approach eases software development but makes dependability a big challenge. Integrating such diverse software items raise issues that traditional testing is not able to exhaustively cope with. In this context, tolerating faults, rather than attempt to detect them solely by testing, is a more suitable solution. This paper proposes a method to support a tailored design of fault tolerance actions for the system being developed. This paper describes system failure behavior through an extensive fault injection campaign to figure out its criticalities and adopt the most appropriate countermeasures to tolerate operational faults. The proposed method is applied to two distinct SOC-enabling technologies. Results show how the achieved findings allow designers to understand the system failure behavior and plan fault tolerance.

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Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Electronics ◽

10.3390/electronics9122074 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2074

Author(s):

J.-Carlos Baraza-Calvo ◽

Joaquín Gracia-Morán ◽

Luis-J. Saiz-Adalid ◽

Daniel Gil-Tomás ◽

Pedro-J. Gil-Vicente

Keyword(s):

Fault Tolerance ◽

Error Correction ◽

Error Detection ◽

Fault Injection ◽

Error Correction Codes ◽

Transient Faults ◽

Tolerance Mechanism ◽

Intermittent Faults ◽

Risc Processor ◽

Simulation Based

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

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Automated Testing of Ultrawideband Positioning for Autonomous Driving

Journal of Robotics ◽

10.1155/2020/9345360 ◽

2020 ◽

Vol 2020 ◽

pp. 1-15

Author(s):

Benjamin Vedder ◽

Bo Joel Svensson ◽

Jonny Vinter ◽

Magnus Jonsson

Keyword(s):

Fault Tolerance ◽

Real Time ◽

Autonomous Vehicles ◽

Fault Injection ◽

Autonomous Driving ◽

Automated Testing ◽

Test Cases ◽

Positioning System ◽

Novel Approach ◽

Driving Model

Autonomous vehicles need accurate and dependable positioning, and these systems need to be tested extensively. We have evaluated positioning based on ultrawideband (UWB) ranging with our self-driving model car using a highly automated approach. Random drivable trajectories were generated, while the UWB position was compared against the Real-Time Kinematic Satellite Navigation (RTK-SN) positioning system which our model car also is equipped with. Fault injection was used to study the fault tolerance of the UWB positioning system. Addressed challenges are automatically generating test cases for real-time hardware, restoring the state between tests, and maintaining safety by preventing collisions. We were able to automatically generate and carry out hundreds of experiments on the model car in real time and rerun them consistently with and without fault injection enabled. Thereby, we demonstrate one novel approach to perform automated testing on complex real-time hardware.

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