Acyclic orientations for deadlock prevention in interconnection networks

1997 ◽  
pp. 52-64 ◽  
Author(s):  
Jean-Claude Bermond ◽  
Miriam Di Ianni ◽  
Michele Flammini ◽  
Stephane Perennes
Keyword(s):  
Interconnection Networks ◽  
Deadlock Prevention ◽  
Acyclic Orientations

scholarly journals Deadlock prevention by acyclic orientations

2003 ◽  
Vol 129 (1) ◽  
pp. 31-47 ◽  
Author(s):  
Jean-Claude Bermond ◽  
Miriam Di Ianni ◽  
Michele Flammini ◽  
Stéphane Pérennès
Keyword(s):  
Deadlock Prevention ◽  
Acyclic Orientations

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Dynamic probe based strategy for deadlock prevention in distributed systems

2009 ◽  
Vol 29 (1) ◽  
pp. 209-212 ◽  
Author(s):  
Chen LI ◽  
Dun-lu PENG
Keyword(s):  
Distributed Systems ◽  
Deadlock Prevention

Quantitative Reliability Analysis of Redundant Multistage Interconnection Networks

1991 ◽  
Author(s):  
Nita M. Kini ◽  
Anup Kumar ◽  
Dharma P. Agrawal
Keyword(s):  
Reliability Analysis ◽  
Interconnection Networks ◽  
Multistage Interconnection Networks

Concurrent error detection in VLSI interconnection networks

1983 ◽  
Vol 11 (3) ◽  
pp. 309-315 ◽  
Author(s):  
W. Kent Fuchs ◽  
Jacob A. Abraham ◽  
Kuang-Hua Huang
Keyword(s):  
Error Detection ◽  
Interconnection Networks ◽  
Concurrent Error Detection

On a Realization of Multi-terminal Universal Interconnection Networks using Contact Switches

2020 ◽  
Author(s):  
Tsutomu Sasao ◽  
Takashi Matsubara ◽  
Katsufumi Tsuji ◽  
Yoshiaki Koga
Keyword(s):  
Interconnection Networks
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