Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse

In this article, we propose a hardware accelerator design using ferroelectric transistor (FeFET)-based hybrid precision synapse (HPS) for deep neural network (DNN) on-chip training. The drain erase scheme for FeFET programming is incorporated for both FeFET HPS design and FeFET buffer design. By using drain erase, high-density FeFET buffers can be integrated onchip to store the intermediate input-output activations and gradients, which reduces the energy consuming off-chip DRAM access. Architectural evaluation results show that the energy efficiency could be improved by 1.2× ∼ 2.1×, 3.9× ∼ 6.0× compared to the other HPS-based designs and emerging non-volatile memory baselines, respectively. The chip area is reduced by 19% ∼ 36% compared with designs using SRAM on-chip buffer even though the capacity of FeFET buffer is increased. Besides, by utilizing drain erase scheme for FeFET programming, the chip area is reduced by 11% ∼ 28.5% compared with the designs using body erase scheme.

CIB-HIER

Hierarchical organization is widely used in high-radix routers to enable efficient scaling to higher switch port count. A general-purpose hierarchical router must be symmetrically designed with the same input buffer depth, resulting in a large amount of unused input buffers due to the different link lengths. Sharing input buffers between different input ports can improve buffer utilization, but the implementation overhead also increases with the number of shared ports. Previous work allowed input buffers to be shared among all router ports, which maximizes the buffer utilization but also introduces higher implementation complexity. Moreover, such design can impair performance when faced with long packets, due to the head-of-line blocking in intermediate buffers. In this work, we explain that sharing unused buffers between a subset of router ports is a more efficient design. Based on this observation, we propose Centralized Input Buffer Design in Hierarchical High-radix Routers (CIB-HIER), a novel centralized input buffer design for hierarchical high-radix routers. CIB-HIER integrates multiple input ports onto a single tile and organizes all unused input buffers in the tile as a centralized input buffer. CIB-HIER only allows the centralized input buffer to be shared between ports on the same tile, without introducing additional intermediate virtual channels or global scheduling circuits. Going beyond the basic design of CIB-HIER, the centralized input buffer can be used to relieve the head-of-line blocking caused by shallow intermediate buffers, by stashing long packets in the centralized input buffer. Experimental results show that CIB-HIER is highly effective and can significantly increase the throughput of high-radix routers.

Quantifying the Importance of Preferential Flow in a Riparian Buffer

HighlightsRiparian buffers and vegetative filter strips are uniquely susceptible to preferential flow.An innovative method is proposed to partition infiltration into matrix and macropore domains.Riparian buffer matrix and plot-scale infiltration experiments were simulated with HYDRUS-1D and VFSMOD.Preferential flow accounted for 32% to 47% of infiltration depending on hydrologic conditions.Preferential flow mechanisms should be incorporated into riparian buffer design tools and models.Abstract. Riparian buffers are uniquely susceptible to preferential flow due to the abundance of root channels, biological activity, and frequent wetting and drying cycles. Previous research has indicated such susceptibility and even measured the connectivity of preferential flow pathways with adjacent streams and rivers. However, limited research has attempted to partition the riparian buffer infiltration between matrix and preferential flow domains. The objectives of this research were to develop an innovative method to quantify soil matrix infiltration at the plot scale, develop a method to partition infiltration into matrix and macropore infiltration at the plot scale, and then use these methods to quantify the significance of macropore infiltration at a riparian buffer site. This research further demonstrated the importance of considering preferential flow processes in design tools and models to evaluate riparian buffer effectiveness. Sprinkler and runon field experiments were conducted at an established riparian buffer site with sandy loam soil. Trenches were installed and instrumented with soil moisture sensors along the width of the riparian buffer (i.e., along the flow path toward the stream) for detecting non-uniform flow patterns due to preferential flow. Riparian buffer parameters, including soil hydraulic parameters, were estimated using HYDRUS-1D for the sprinkler experiments and VFSMOD for the runon experiments. This research partitioned the infiltration into matrix and preferential flow domains by assuming negligible exchange of water between the soil matrix and preferential flow pathways in comparison to the magnitude of soil matrix flow. For these experimental conditions with 0.20 to 0.48 L s-1 of runon and initial soil water contents of 0.29 to 0.32 cm3 cm-3, preferential flow accounted for at least 27% to 32% of the total runon water entering the riparian buffer. This corresponded to approximately 32% to 47% of the total infiltration. While increasing the riparian buffer plot soil hydraulic conductivity in single-porosity models can adequately predict the total infiltration and therefore the surface outflow from the buffer, design tools and models should specifically consider preferential flow processes to improve predictive power regarding the actual infiltration processes and correspondingly the non-equilibrium flow and solute transport mechanisms. Keywords: Flow partitioning, HYDRUS, Matrix flow, Preferential flow, Riparian buffer, VFSMOD.