From T(m) triangular graphs to single-error-correcting codes

2006 ◽  
pp. 5-12
Author(s):  
J. M. Basart ◽  
L. Huguet
Keyword(s):  
Error Correcting Codes ◽  
Single Error

scholarly journals A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 709
Author(s):  
Abhishek Das ◽  
Nur A. Touba
Keyword(s):  
Optimization Technique ◽  
Error Correcting Code ◽  
Latin Square ◽  
Error Correcting Codes ◽  
Trade Off ◽  
Cache Memories ◽  
Hamming Codes ◽  
Single Error ◽  
Memory Overhead ◽  
On Chip

Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.

Single error-correcting codes for asymmetric binary channels

1959 ◽  
Vol 5 (2) ◽  
pp. 62-66 ◽  
Author(s):  
Wan Kim ◽  
C. Freiman
Keyword(s):  
Error Correcting Codes ◽  
Single Error ◽  
Binary Channels

Single-error-correcting codes for constant-weight data words

1965 ◽  
Vol 11 (1) ◽  
pp. 132-141 ◽  
Author(s):  
W. Kautz ◽  
B. Elspas
Keyword(s):  
Error Correcting Codes ◽  
Constant Weight ◽  
Single Error ◽  
Weight Data

scholarly journals Improved lower bounds on sizes of single-error correcting codes

2006 ◽  
Vol 42 (1) ◽  
pp. 67-72 ◽  
Author(s):  
Simon Litsyn ◽  
Beniamin Mounits
Keyword(s):  
Lower Bounds ◽  
Error Correcting Codes ◽  
Single Error

scholarly journals New family of single-error correcting codes

1970 ◽  
Vol 16 (6) ◽  
pp. 717-719 ◽  
Author(s):  
N. Sloane ◽  
D. Whitehead
Keyword(s):  
Error Correcting Codes ◽  
Single Error ◽  
New Family

New single-error-correcting codes

1996 ◽  
Vol 42 (4) ◽  
pp. 1261-1262 ◽  
Author(s):  
P.R.J. Ostergard ◽  
M.K. Kaikkonen
Keyword(s):  
Error Correcting Codes ◽  
Single Error

A NEW GENETIC DESIGN FOR ERROR CORRECTING CODE FOR POWER MINIMIZATION

2008 ◽  
Vol 17 (05) ◽  
pp. 773-783 ◽  
Author(s):  
HEESUNG LEE ◽  
EUNTAI KIM
Keyword(s):  
Optimization Problem ◽  
Soft Errors ◽  
Error Correcting Code ◽  
Error Correcting Codes ◽  
Power Minimization ◽  
Genetic Operators ◽  
Embedded Memory ◽  
Single Error ◽  
Error Detecting ◽  
Check Circuit

Error correcting codes (ECCs) are commonly used as a protection against the soft errors. Single error correcting and double error detecting (SEC–DED) codes are generally used for this purpose. Such circuits are widely used in industry in all types of memory, including caches and embedded memory. In this paper, a new genetic design for ECC is proposed to perform SEC–DED in the memory check circuit. The design is aimed at finding the implementation of ECC which consumes minimal power. We formulate the ECC design into a permutable optimization problem and employ special genetic operators appropriate for this formulation. Experiments are performed to demonstrate the performance of the proposed method.

scholarly journals Perfect Single Error-Correcting Codes in the Johnson Scheme

2006 ◽  
Vol 52 (10) ◽  
pp. 4670-4672 ◽  
Author(s):  
D.M. Gordon
Keyword(s):  
Error Correcting Codes ◽  
Single Error ◽  
Johnson Scheme

Erratum: Multilevel single-error-correcting codes

1974 ◽  
Vol 10 (19) ◽  
pp. 408
Author(s):  
P.G. Farrell ◽  
Z. Al-Bandar
Keyword(s):  
Error Correcting Codes ◽  
Single Error
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