High-level synthesis for dynamically reconfigurable hardware/software systems

1998 ◽  
pp. 288-297 ◽  
Author(s):  
Rainer Kress ◽  
Andreas Pyttel
Keyword(s):  
Reconfigurable Hardware ◽  
High Level Synthesis ◽  
Software Systems ◽  
Dynamically Reconfigurable ◽  
High Level

scholarly journals High-level Synthesis Challenges for Mapping a Complete Program on a Dynamically Reconfigurable Processor

2010 ◽  
Vol 3 ◽  
pp. 91-104 ◽  
Author(s):  
Takao Toi ◽  
Noritsugu Nakamura ◽  
Yoshinosuke Kato ◽  
Toru Awashima ◽  
Kazutoshi Wakabayashi
Keyword(s):  
High Level Synthesis ◽  
Reconfigurable Processor ◽  
Dynamically Reconfigurable ◽  
High Level ◽  
Complete Program

High-Level Synthesis Challenges and Solutions for a Dynamically Reconfigurable Processor

2006 ◽  
Author(s):  
Takao Toi ◽  
Noritsugu Nakamura ◽  
Yoshinosuke Kato ◽  
Toru Awashima ◽  
Kazutoshi Wakabayashi ◽  
...  
Keyword(s):  
High Level Synthesis ◽  
Reconfigurable Processor ◽  
Dynamically Reconfigurable ◽  
High Level

scholarly journals A Novel FPGA-Based Intent Recognition System Utilizing Deep Recurrent Neural Networks

Electronics ◽  
2021 ◽  
Vol 10 (20) ◽  
pp. 2495
Author(s):  
Kyriaki Tsantikidou ◽  
Nikolaos Tampouratzis ◽  
Ioannis Papaefstathiou
Keyword(s):  
Neural Network ◽  
Quality Of Life ◽  
Recurrent Neural Networks ◽  
Recognition System ◽  
Reconfigurable Hardware ◽  
High Level Synthesis ◽  
Intent Recognition ◽  
High Level ◽  
And Control

In recent years, systems that monitor and control home environments, based on non-vocal and non-manual interfaces, have been introduced to improve the quality of life of people with mobility difficulties. In this work, we present the reconfigurable implementation and optimization of such a novel system that utilizes a recurrent neural network (RNN). As demonstrated in the real-world results, FPGAs have proved to be very efficient when implementing RNNs. In particular, our reconfigurable implementation is more than 150× faster than a high-end Intel Xeon CPU executing the reference inference tasks. Moreover, the proposed system achieves more than 300× the improvements, in terms of energy efficiency, when compared with the server CPU, while, in terms of the reported achieved GFLOPS/W, it outperforms even a server-tailored GPU. An additional important contribution of the work discussed in this study is that the implementation and optimization process demonstrated can also act as a reference to anyone implementing the inference tasks of RNNs in reconfigurable hardware; this is further facilitated by the fact that our C++ code, which is tailored for a high-level-synthesis (HLS) tool, is distributed in open-source, and can easily be incorporated to existing HLS libraries.

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