A segmentation layout guarding technique to mitigate parasitic capacitance of integrated resistors
2017 ◽
Vol 93
(2)
◽
pp. 237-243
◽
Jianing Wang
◽
Sjoerd W.H. de Haan
◽
J.A. Ferreira
◽
Peter Luerkens
2010 ◽
Vol 57
(9)
◽
pp. 3109-3117
◽
Konrad Miehle
◽
Thomas P. Weldon
◽
Ryan S. Adams
◽
Kasra Daneshvar
2009 ◽
Vol 53
(9)
◽
pp. 1041-1045
◽
Xi Liu
◽
Xiaoshi Jin
◽
Jong-Ho Lee
T. Sato
◽
S. Takagi
◽
N. Fujii
◽
Y. Hashimoto
◽
K. Sakata
◽
...
Fu-Jen Hsu
◽
Chien-Chung Hung
◽
Kuo-Ting Chu
◽
Lurng-Shehng Lee
◽
Chwan-Ying Lee
Zhao Yuan
◽
Balaji Narayanasamy
◽
Zhongjing Wang
◽
Yalin Wang
◽
Asif Imran Emon
◽
...
Hee Sung Lee
◽
Kwang Kyu Hwang
◽
Dong Min Kang
◽
Seong Jun Cho
◽
Chul Woo Byeon
◽
...