A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>

A Computationally Efficient Compact Model for Ferroelectric FinFETs Switching with Asymmetric Non-Periodic Input Signals

<div>In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric Fin-FETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an R-C circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of 7nm FinFET.</div>

Compact Model for Bipolar and Multilevel Resistive Switching in Metal-Oxide Memristors

The article presents the results of the development and study of a combined circuitry (compact) model of thin metal oxide films based memristive elements, which makes it possible to simulate both bipolar switching processes and multilevel tuning of the memristor conductivity taking into account the statistical variability of parameters for both device-to-device and cycle-to-cycle switching. The equivalent circuit of the memristive element and the equation system of the proposed model are considered. The software implementation of the model in the MATLAB has been made. The results of modeling static current-voltage characteristics and transient processes during bipolar switching and multilevel turning of the conductivity of memristive elements are obtained. A good agreement between the simulation results and the measured current-voltage characteristics of memristors based on TiOx films (30 nm) and bilayer TiO2/Al2O3 structures (60 nm/5 nm) is demonstrated.

Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks

Since the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a $$n^+$$ n + plate, without requiring any p-doped region to contact the string channel and therefore allowing to simplify the manufacturing process and increase the array integration density. For those reasons, the understanding of the physical phenomena occurring in the string when GIDL is triggered is important for the proper design of the cell structure and of the voltage waveforms adopted during erase. Even though a detailed comprehension of the GIDL phenomenology can be achieved by means of technology computer-aided design (TCAD) simulations, they are usually time and resource consuming, especially when realistic string structures with many word-lines (WLs) are considered. In this chapter, an analysis of the GIDL-assisted erase in 3–D VC nand memory arrays is presented. First, the evolution of the string potential and GIDL current during erase is investigated by means of TCAD simulations; then, a compact model able to reproduce both the string dynamics and the threshold voltage transients with reduced computational effort is presented. The developed compact model is proven to be a valuable tool for the optimization of the array performance during erase assisted by GIDL. Then, the idea of taking advantage of GIDL for the erase operation is exported to the context of spiking neural networks (SNNs) based on NOR Flash memory arrays, which require operational schemes that allow single-cell selectivity during both cell program and cell erase. To overcome the block erase typical of nor Flash memory arrays based on Fowler-Nordheim tunneling, a new erase scheme that triggers GIDL in the NOR Flash cell and exploits hot-hole injection (HHI) at its drain side to accomplish the erase operation is presented. Using that scheme, spike-timing dependent plasticity (STDP) is implemented in a mainstream NOR Flash array and array learning is successfully demonstrated in a prototype SNN. The achieved results represent an important step for the development of large-scale neuromorphic systems based on mature and reliable memory technologies.

JDAT: Joint-Dimension-Aware Transformer with Strong Flexibility for EEG Emotion Recognition

<div>Electroencephalography (EEG) emotion recognition, an important task in Human-Computer Interaction (HCI), has made a great breakthrough with the help of deep learning algorithms. Although the application of attention mechanism on conventional models has improved its performance, most previous research rarely focused on multiplex EEG features jointly, lacking a compact model with unified attention modules. This study proposes Joint-Dimension-Aware Transformer (JDAT), a robust model based on squeezed Multi-head Self-Attention (MSA) mechanism for EEG emotion recognition. The adaptive squeezed MSA applied on multidimensional features enables JDAT to focus on diverse EEG information, including space, frequency, and time. Under the joint attention, JDAT is sensitive to the complicated brain activities, such as signal activation, phase-intensity couplings, and resonance. Moreover, its gradually compressed structure contains no recurrent or parallel modules, greatly reducing the memory and complexity, and accelerating the inference process. The proposed JDAT is evaluated on DEAP, DREAMER, and SEED datasets, and experimental results show that it outperforms state-of-the-art methods along with stronger flexibility.</div>

A Dynamic Compact Model for Ferroelectric Capacitance

A non-quasi-static model for ferroelectric capacitance is developed in this letter. A state transition in the voltage and time domains between two polarization states is formulated first. The quasi-static model is derived from the state transition of voltage domain, and supports the minor loops. Different from the Preisach model, an initial state is supported, and the modulated coercive voltages are responsible for minor loops. The non-quasi -static model is then derived with the state transition in the time domain, similar to a relaxation approximation in MOSFET modeling. The non-quasi-static model reproduces the saturation loop, minor loops, the frequency-dependent characteristics of measured ferroelectric capacitances, with their origins explained from polarization switching relaxation. The pulse width dependent switching is well reproduced with the model.