A Framework for Configurable Joint-Scan Design-for-Test Architecture

2021 ◽  
Author(s):  
Jaynarayan T. Tudu ◽  
Satyadev Ahlawat ◽  
Sonali Shukla ◽  
Virendra Singh
Keyword(s):  
Design For Test ◽  
Scan Design ◽  
Test Architecture

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

2007 ◽  
Author(s):  
Xuan-Tu Tran ◽  
Jean Durupt ◽  
Yvain Thonnart ◽  
Francois Bertrand ◽  
Vincent Beroulle ◽  
...  
Keyword(s):  
Design For Test ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip ◽  
Test Architecture

3D Design‐for‐Test Architecture

2019 ◽  
pp. 253-280
Author(s):  
Erik Jan Marinissen ◽  
Mario Konijnenburg ◽  
Jouke Verbree ◽  
Chun‐Chuan Chi ◽  
Sergej Deutsch ◽  
...  
Keyword(s):  
Design For Test ◽  
3D Design ◽  
Test Architecture

The design for test architecture in digital section of the ATLAS FE-I4 chip

2011 ◽  
Vol 6 (01) ◽  
pp. C01090-C01090 ◽  
Author(s):  
V Zivkovic ◽  
J -D Schipper ◽  
R Kluit ◽  
M Garcia-Sciveres ◽  
A Mekkaoui ◽  
...  
Keyword(s):  
Design For Test ◽  
Test Architecture

Hybrid Test Application in Partial Skewed-Load Scan Design

2011 ◽  
Vol E94-A (12) ◽  
pp. 2571-2578
Author(s):  
Yuki YOSHIKAWA ◽  
Tomomi NUWA ◽  
Hideyuki ICHIHARA ◽  
Tomoo INOUE
Keyword(s):  
Scan Design ◽  
Test Application ◽  
Hybrid Test
Sign in / Sign up

Export Citation Format

Share Document