A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors

2003 ◽  
Author(s):  
I. Parulkar ◽  
T. Ziaja ◽  
R. Pendurkar ◽  
A. D'Souza ◽  
A. Majumdar
Keyword(s):  
Low Cost ◽  
Design For Test ◽  
Test Architecture

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip

2007 ◽  
Author(s):  
Xuan-Tu Tran ◽  
Jean Durupt ◽  
Yvain Thonnart ◽  
Francois Bertrand ◽  
Vincent Beroulle ◽  
...  
Keyword(s):  
Design For Test ◽  
Networks On Chip ◽  
Asynchronous Networks ◽  
On Chip ◽  
Test Architecture

3D Design‐for‐Test Architecture

2019 ◽  
pp. 253-280
Author(s):  
Erik Jan Marinissen ◽  
Mario Konijnenburg ◽  
Jouke Verbree ◽  
Chun‐Chuan Chi ◽  
Sergej Deutsch ◽  
...  
Keyword(s):  
Design For Test ◽  
3D Design ◽  
Test Architecture

scholarly journals A low-cost concurrent TSV test architecture with lossless test output compression scheme

PLoS ONE ◽  
2019 ◽  
Vol 14 (8) ◽  
pp. e0221043 ◽  
Author(s):  
Young-woo Lee ◽  
Hyunchan Lim ◽  
Sungyoul Seo ◽  
Keewon Cho ◽  
Sungho Kang
Keyword(s):  
Low Cost ◽  
Compression Scheme ◽  
Test Architecture

scholarly journals A Low-Cost Self-Test Architecture Integrated With PRESENT Cipher Core

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 46045-46058
Author(s):  
Zeeshan Haider ◽  
Khalid Javeed ◽  
Mei Song ◽  
Xiaojun Wang
Keyword(s):  
Low Cost ◽  
Self Test ◽  
Test Architecture

A Framework for Configurable Joint-Scan Design-for-Test Architecture

2021 ◽  
Author(s):  
Jaynarayan T. Tudu ◽  
Satyadev Ahlawat ◽  
Sonali Shukla ◽  
Virendra Singh
Keyword(s):  
Design For Test ◽  
Scan Design ◽  
Test Architecture

Low cost test architecture for mixed-signal integrated circuits

2014 ◽  
Author(s):  
Julio L. da Silva ◽  
Emerson Camargo ◽  
Douglas Foster ◽  
Sandro T. Coelho ◽  
Antonio G. de Oliveira ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Cost ◽  
Mixed Signal ◽  
Test Architecture
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