Power Analysis and Implementation of Low-Power Design for Test Architecture for UltraSPARC Chip Multiprocessor

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit. The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.

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The low power design of SM4 cipher with resistance to differential power analysis

Sixteenth International Symposium on Quality Electronic Design ◽

10.1109/isqed.2015.7085471 ◽

2015 ◽

Cited By ~ 7

Author(s):

Yanbo Niu ◽

Anping Jiang

Keyword(s):

Low Power ◽

Power Analysis ◽

Low Power Design ◽

Differential Power Analysis

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Low power synthesis for asynchronous FIFO using unified power format (UPF)

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.8.10315 ◽

2018 ◽

Vol 7 (2.8) ◽

pp. 7

Author(s):

Avinash Yadlapati ◽

K Hari Kishore

Keyword(s):

Low Power ◽

Logic Synthesis ◽

Reducing Power ◽

Low Power Design ◽

Design Flow ◽

Functional Verification ◽

Design For Test ◽

Asic Design ◽

The Common ◽

Low Power Synthesis

Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.

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Low-power design-for-test implementation on phase-locked loop design

Measurement and Control ◽

10.1177/0020294019858089 ◽

2019 ◽

Vol 52 (7-8) ◽

pp. 995-1001

Author(s):

Avinash Yadlapati ◽

Hari Kishore Kakarla

Keyword(s):

Low Power ◽

Test Pattern ◽

Low Power Design ◽

Pattern Generation ◽

Test Pattern Generation ◽

Design For Test ◽

Automatic Test Pattern Generation ◽

Clock Frequency ◽

Automatic Test ◽

Register Transfer

Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-power technology in the phase of register transfer logic design, functional verification, register transfer logic and physical synthesis and physical design. Design for test is not an exception to this. The low-power design-for-test techniques can be applied at various levels of the design-for-test flow as in the scan insertion stage, automatic test pattern generation simulations stage, testing stage, and so on. Some of the reasons for the high-power utilization in the design-for-test phase can be due to the external circuitry being inserted during the design phase and not used in the functional mode. The complete circuit will be active in the test mode only. In this paper, the focus will be primarily on reducing the power during the automatic test pattern generation scan synthesis phase. All the scan flops are connected by a common scan clock with a fixed frequency. The intention of this study is to divide the clock frequency by half and make sure that the power is reduced without affecting any timing violations. Since the scan clock frequency is low, it can be further divided to ensure that power is reduced without affecting the testing process of the chip.

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