Mobile Networks-on-Chip Mapping Algorithms for Optimization of Latency and Energy Consumption

2021 ◽  
Author(s):  
Arvind Kumar ◽  
Vivek Kumar Sehgal ◽  
Gaurav Dhiman ◽  
S. Vimal ◽  
Ashutosh Sharma ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Mobile Networks ◽  
Mapping Algorithms ◽  
Networks On Chip ◽  
On Chip

Comparison of network-on-chip mapping algorithms targeting low energy consumption

2008 ◽  
Vol 2 (6) ◽  
pp. 471 ◽  
Author(s):  
C.A.M. Marcon ◽  
E.I. Moreno ◽  
N.L.V. Calazans ◽  
F.G. Moraes
Keyword(s):  
Energy Consumption ◽  
Network On Chip ◽  
Low Energy ◽  
Mapping Algorithms ◽  
Low Energy Consumption ◽  
On Chip

A Communication Probability-Based Mapping Algorithm for Mesh-Based Network-on-Chip Systems

2018 ◽  
Vol 27 (14) ◽  
pp. 1850226
Author(s):  
Jin Sun ◽  
Yi Zhang
Keyword(s):  
Energy Consumption ◽  
Optimization Model ◽  
Search Space ◽  
Network On Chip ◽  
Task Graph ◽  
Mapping Procedure ◽  
Mapping Algorithms ◽  
Mapping Algorithm ◽  
On Chip ◽  
Communication Locality

Network-on-chip (NoC) mapping algorithms significantly affect NoC system performance in terms of communication cost and energy consumption. For a specific application represented by a task graph, this paper proposes an energy-efficient mapping algorithm that searches for the mapping decision with best communication locality and therefore lowest energy consumption. To this end, we formulate the concerned mapping problem as an optimization model, and propose an effective meta-heuristic algorithm to solve the formulated optimization model. During the mapping procedure, we employ a simulation-free, communication probability-based energy model to evaluate the quality of each candidate mapping. By iteratively updating the best explored mapping decision using a meta-heuristic search strategy, the mapping procedure can eventually identify an mapping decision with optimal energy efficiency in the search space. The proposed mapping algorithm has been verified on NoC systems of different sizes using a variety of benchmark applications. Simulation results demonstrate that the mapping decision produced by this algorithm achieves an up to 23% energy reduction compared with the traditional round-robin strategy.

scholarly journals Exploration of Temperature Constraints for Thermal-Aware Mapping of 3D Networks-on-Chip

2013 ◽  
Vol 4 (3) ◽  
pp. 42-60 ◽  
Author(s):  
Parisa Khadem Hamedani ◽  
Natalie Enright Jerger ◽  
Shaahin Hessabi ◽  
Hamid Sarbazi-Azad
Keyword(s):  
Complexity Analysis ◽  
Major Effect ◽  
Peak Temperature ◽  
Thermal Calculation ◽  
Mapping Algorithms ◽  
Networks On Chip ◽  
Mapping Algorithm ◽  
On Chip ◽  
Power Delay Product ◽  
3D Networks

This paper proposes three ILP-based static thermal-aware mapping algorithms for 3D Networks-on-Chip (NoC). With these three mapping algorithms, the authors explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, the authors show that the first algorithm, an optimal one, is not suitable for 3D NoCs. Therefore, the authors develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. According to simulation results, mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This peak temperature reduction comes at the price of a higher power-delay product. The authors’ exploration shows that considering power balancing early in the mapping algorithm does not affect chip temperature. Moreover, the authors show that considering explicit performance constraints in the thermal mapping has no major effect on performance.

Fuzzy-based mapping algorithms to design networks-on-chip

2016 ◽  
Vol 31 (1) ◽  
pp. 27-43 ◽  
Author(s):  
Mehdi Taassori ◽  
Sadegh Niroomand ◽  
Sener Uysal ◽  
Abdollah Hadi-Vencheh ◽  
Béla Vizvári
Keyword(s):  
Mapping Algorithms ◽  
Networks On Chip ◽  
On Chip

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

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