Spatio-Temporal Graph Attention Embedding for Joint Crowd Flow and Transition Predictions

Crowd mobility prediction, in particular, forecasting flows at and transitions across different locations, is essential for crowd analytics and management in spacious environments featured with large gathering. We propose GAEFT, a novel crowd mobility analytics system based on the multi-task graph attention neural network to forecast crowd flows (inflows/outflows) and transitions. Specifically, we leverage the collective and sanitized campus Wi-Fi association data provided by our university information technology service and conduct a relatable case study. Our comprehensive data analysis reveals the important challenges of sparsity and skewness, as well as the complex spatio-temporal variations within the crowd mobility data. Therefore, we design a novel spatio-temporal clustering method to group Wi-Fi access points (APs) with similar transition features, and obtain more regular mobility features for model inputs. We then propose an attention-based graph embedding design to capture the correlations among the crowd flows and transitions, and jointly predict the AP-level flows as well as transitions across buildings and clusters through a multi-task formulation. Extensive experimental studies using more than 28 million association records collected during 2020-2021 academic year validate the excellent accuracy of GAEFT in forecasting dynamic and complex crowd mobility.

Path Aggregation Model for Attributed Network Embedding with a Smart Random Walk

Network embedding has attracted a surge of attention recently. In this field, how to preserve high-order proximity has long been a difficult task. Graph convolutional network (GCN) and random walk-based approaches can preserve high-order proximity to a certain extent. However, they partially concentrate on the aggregation process and sampling process respectively. Path aggregation methods combine the merits of GCN and random walk, and thus can preserve more high-order information and achieve better performance. However, path aggregation framework has not been applied in attributed network embedding yet. In this paper, we propose a path aggregation model for attributed network embedding, with two main contributions. First, we claim that there always exists implicit edge weight in networks, and design a tweaked random walk algorithm to sample paths accordingly. Second, we propose a path aggregation framework dealing with both nodes and attributes. Extensive experimental results show that our proposal outperforms the cutting-edge baselines on downstream tasks, such as node clustering, node classification, and link prediction.

SLAQA

Continuous demands for higher performance and reliability within stringent resource budgets is driving a shift from homogeneous to heterogeneous processing platforms for the implementation of today’s cyber-physical systems (CPSs). These CPSs are typically represented as Directed-acyclic Task Graph (DTG) due to the complex interactions between their functional components that are often distributed in nature. In this article, we consider the problem of scheduling a real-time application modelled as a single DTG, where tasks may have multiple implementations designated as quality-levels, with higher quality-levels producing more accurate results and contributing to higher rewards/Quality-of-Service for the system. First, we introduce an optimal solution using Integer Linear Programming (ILP) for a DTG with multiple quality-levels, to be executed on a heterogeneous distributed platform . However, this ILP-based optimal solution exhibits high computational complexity and does not scale for moderately large problem sizes. Hence, we propose two low-overhead heuristic algorithms called Global Slack Aware Quality-level Allocator ( G-SLAQA ) and Total Slack Aware Quality-level Allocator ( T-SLAQA ), which are able to produce satisfactorily efficient as well as fast solutions within a reasonable time. G-SLAQA , the baseline heuristic, is greedier and faster than its counter-part T-SLAQA , whose performance is at least as efficient as G-SLAQA . The efficiency of all the proposed schemes have been extensively evaluated through simulation-based experiments using benchmark and randomly generated DTGs. Through the case study of a real-world automotive traction controller , we generate schedules using our proposed schemes to demonstrate their practical applicability.

Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems

Existing software development methodologies mostly assume that an application runs on a single device without concern about the non-functional requirements of an embedded system such as latency and resource consumption. Besides, embedded software is usually developed after the hardware platform is determined, since a non-negligible portion of the code depends on the hardware platform. In this article, we present a novel model-based software synthesis framework for parallel and distributed embedded systems. An application is specified as a set of tasks with the given rules for execution and communication. Having such rules enables us to perform static analysis to check some software errors at compile-time to reduce the verification difficulty. Platform-specific programs are synthesized automatically after the mapping of tasks onto processing elements is determined. The proposed framework is expandable to support new hardware platforms easily. The proposed communication code synthesis method is extensible and flexible to support various communication methods between devices. In addition, the fault-tolerant feature can be added by modifying the task graph automatically according to the selected fault-tolerance configurations by the user. The viability of the proposed software development methodology is evaluated with a real-life surveillance application that runs on six processing elements.

Hardware Software Co-Synthesis of Heterogenous Hypercube Architectures for Fault Tolerant Embedded Systems

The hardware-software synthesis of an embedded system's architecture involves the partitioning of a system specification into hardware and software modules so as to meet various non-functional requirements. A designer can specify many non-functional requirements including cost, performance, reliability etc. In this thesis, we present an approach to the hardware-software co-synthesis of embedded systems targeting hypercube topologies. Hypercube topologies provide a flexible and reliable architecture for an embedded device with multiple processing elements. To the best of our knowledge, this is the first time that hypercube topologies have been supported in a co-synthesis algorithm. The co-synthesis approach represented here supports the following features: 1)input in the form of an acrylic periodic task graph with real-time constraints, 2) the pipelining of task graphs, 3) the use of a heterogeneous set of processing elements, 4) Support for fault tolerance through our newly developed group based fault tolerance technique. The co-synthesis algorithm has been applied to two case studies to demonstrate its efficacy.