Performance-driven parallel reconfigurable computing architecture for multi-standard video decoding

2020 ◽  
Vol 79 (41-42) ◽  
pp. 30583-30599
Author(s):  
Chi-Chou Kao
Keyword(s):  
Reconfigurable Computing ◽  
Video Decoding ◽  
Computing Architecture

Compiler Framework for Reconfigurable Computing Architecture

2009 ◽  
Vol E92-C (10) ◽  
pp. 1284-1290 ◽  
Author(s):  
Chongyong YIN ◽  
Shouyi YIN ◽  
Leibo LIU ◽  
Shaojun WEI
Keyword(s):  
Reconfigurable Computing ◽  
Computing Architecture ◽  
Compiler Framework

scholarly journals A Cost Efficiency Analysis and Mechanism for Dynamic Partially Reconfigurable Computing Systems

2021 ◽  
Author(s):  
David Diaz
Keyword(s):  
Reconfigurable Computing ◽  
Cost Efficiency ◽  
Experimental Tests ◽  
Efficiency Analysis ◽  
Efficiency Factor ◽  
Design Stage ◽  
Computing Systems ◽  
Computing Architecture ◽  
Development Costs ◽  
The Cost

Dynamic Partially Reconfigurable Computing Systems have proven to be useful in environments where a multiplicity of tasks is required. These systems used Dynamic Virtual Components (DVCs) for reconfiguration. However, the computing architecture (dedicated, software, hybrid) of the DVC must be selected during the design stage. In this thesis, a mechanism in which we evaluate and analyze the cost efficiency of a DVC based on a cost efficiency factor (CEF) is proposed. Data centric and stream centric experimental tests were performed and the CEF of a 3D stereo-panoramic augmented reality hybrid DVC was de termined. The results show that development costs and number of units to be produced influence the cost efficiency of a DVC. From the results it is concluded that the CEF can be a useful tool for selecting the computing architecture of a DVC, particularly when only a few units are to be deployed.

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