A Novel PageRank Based Fault Handling Strategy for Workflow Scheduling in Cloud Data Centers

Unexpected faults result in unscheduled cloud outage, which negatively affects the completion of workflow tasks in the cloud. This paper presents a novel PageRank based fault handling strategy to rescue workflow tasks at the faulty data center. The proposed approach uses a holistic view and considers the task attributes, the timeline scenario, and the overall cloud performance. A priority assignment system is developed based on the modified PageRank algorithm to prioritise workflow tasks. A Min-Max normalization method is applied to select the target data center and match the timeline at this data center. Additionally, a dynamic PageRank-constrained task scheduling algorithm is proposed to generate the task scheduling solution. The simulation results show that the proposed approach can achieve better fault handling performance, measured by task resilience ratio, workflow resilience ratio and workflow continuity ratio, in both the traditional 3-replica and the image backup cloud environment.

Self-healing trans-cloud applications

Trans-cloud applications consist of multiple interacting components deployed across different cloud providers and at different service layers (IaaS and PaaS). In such complex deployment scenarios, fault handling and recovery need to deal with heterogeneous cloud offerings and to take into account inter-component dependencies. We propose a methodology for self-healing trans-cloud applications from failures occurring in application components or in the cloud services hosting them, both during deployment and while they are being operated. The proposed methodology enables reducing the time application components rely on faulted services, hence residing in “unstable” states where they can suddenly fail in cascade or exhibit erroneous behaviour. We also present an open-source prototype illustrating the feasibility of our proposal, which we have exploited to carry out an extensive evaluation based on controlled experiments and monkey testing.

A Fault Handling Process for Faults in District Heating Customer Installations

Faults in district heating (DH) customer installations cause high return temperatures, which have a negative impact on both current and future district heating systems. Thus, there is a need to detect and correct these faults soon after they occur to minimize their impact on the system. This paper, therefore, suggests a fault handling process for the detection and elimination of faults in DH customer installations. The fault handling process is based on customer data analysis since many faults manifest in customer data. The fault handling process was based on an analysis of the results from the previous fault handling studies, as well as conducting a workshop with experts from the DH industry. During the workshop, different organizational and technical challenges related to fault handling were discussed. The results include a presentation of how the utilities are currently working with fault handling. The results also present an analysis of different organizational aspects that would have to be improved to succeed in fault handling. The paper also includes a suggestion for how a fault handling process based on fault detection using data analysis may be designed. This process may be implemented by utilities in both current and future DH systems that interested in working more actively with faults in their customer installations.

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

This thesis is focused on the modular multilevel converter (MMC) for High-Voltage DC (HVDC) systems. It is an attempt to address the issues associated with the modelling, simulation, control, efficiency, and fault-handling capability of the MMC. Thus, to address the modelling of the MMC, a new and more accurate steady-state harmonic model is proposed. The proposed harmonic model is capable of predicting the amplitude of the harmonic components of the MMC arm voltages, submodule capacitor voltages, and arm currents. Further, based on the proposed harmonic model, a capacitor sizing method is proposed to determine the capacitance of the submodule capacitor for a desired level of voltage variation, without a need for numerical algorithms or graphs used by the existing methods. In addition, the proposed capacitor sizing method can accurately determine the required capacitance even if circulating currents are injected to mitigate dc voltage fluctuations. The thesis also proposes a simple equivalent-circuit-based simulation model for MMC-based HVDC systems, which assumes ideal submodule switches to speed up the simulation, but is nonetheless capable of capturing the transients as well as harmonic components of the voltages and currents. Further, the thesis proposes a simple compensation strategy that calculates the magnitude of the second harmonic component of an arm voltage, and uses the calculated value as a feedforward signal to cancel the circulating current of the corresponding MMC leg. The proposed feedforward compensation strategy, if combined with a closed-loop circulating current suppression strategy, greatly mitigates the possibility of control saturation and, also, results in better damped closed-loop dynamics. Finally, the thesis proposes two new MMC topologies for enhanced efficiency and dc-side fault handling capability. In the first proposed topology, that is the lattice modular multilevel converter (LMMC), the entire MMC arm is modified to accommodate networks that allow shortcuts between the arm capacitors, thus, reducing conduction power losses of the converter. In the second topology proposed, however, only the submodule is modified. In the proposed submodule topology, referred to as lattice submodule (LSM), the conduction power losses are decreased, as it is the case for the LMMC, with the difference that the voltage stress in the switches are also reduced. Keywords: Control, lattice modular multilevel converter, lattice submodule, modelling, modular multilevel converter, simulation model.

Modelling, simulation, control, and enhanced topologies for the modular multilevel converter for high-voltage DC (HVDC) applications

This thesis is focused on the modular multilevel converter (MMC) for High-Voltage DC (HVDC) systems. It is an attempt to address the issues associated with the modelling, simulation, control, efficiency, and fault-handling capability of the MMC. Thus, to address the modelling of the MMC, a new and more accurate steady-state harmonic model is proposed. The proposed harmonic model is capable of predicting the amplitude of the harmonic components of the MMC arm voltages, submodule capacitor voltages, and arm currents. Further, based on the proposed harmonic model, a capacitor sizing method is proposed to determine the capacitance of the submodule capacitor for a desired level of voltage variation, without a need for numerical algorithms or graphs used by the existing methods. In addition, the proposed capacitor sizing method can accurately determine the required capacitance even if circulating currents are injected to mitigate dc voltage fluctuations. The thesis also proposes a simple equivalent-circuit-based simulation model for MMC-based HVDC systems, which assumes ideal submodule switches to speed up the simulation, but is nonetheless capable of capturing the transients as well as harmonic components of the voltages and currents. Further, the thesis proposes a simple compensation strategy that calculates the magnitude of the second harmonic component of an arm voltage, and uses the calculated value as a feedforward signal to cancel the circulating current of the corresponding MMC leg. The proposed feedforward compensation strategy, if combined with a closed-loop circulating current suppression strategy, greatly mitigates the possibility of control saturation and, also, results in better damped closed-loop dynamics. Finally, the thesis proposes two new MMC topologies for enhanced efficiency and dc-side fault handling capability. In the first proposed topology, that is the lattice modular multilevel converter (LMMC), the entire MMC arm is modified to accommodate networks that allow shortcuts between the arm capacitors, thus, reducing conduction power losses of the converter. In the second topology proposed, however, only the submodule is modified. In the proposed submodule topology, referred to as lattice submodule (LSM), the conduction power losses are decreased, as it is the case for the LMMC, with the difference that the voltage stress in the switches are also reduced. Keywords: Control, lattice modular multilevel converter, lattice submodule, modelling, modular multilevel converter, simulation model.

Clustering error messages produced by distributed computing infrastructure during the processing of high energy physics data

Large-scale distributed computing infrastructures ensure the operation and maintenance of scientific experiments at the LHC: more than 160 computing centers all over the world execute tens of millions of computing jobs per day. ATLAS — the largest experiment at the LHC — creates an enormous flow of data which has to be recorded and analyzed by a complex heterogeneous and distributed computing environment. Statistically, about 10–12% of computing jobs end with a failure: network faults, service failures, authorization failures, and other error conditions trigger error messages which provide detailed information about the issue, which can be used for diagnosis and proactive fault handling. However, this analysis is complicated by the sheer scale of textual log data, and often exacerbated by the lack of a well-defined structure: human experts have to interpret the detected messages and create parsing rules manually, which is time-consuming and does not allow identifying previously unknown error conditions without further human intervention. This paper is dedicated to the description of a pipeline of methods for the unsupervised clustering of multi-source error messages. The pipeline is data-driven, based on machine learning algorithms, and executed fully automatically, allowing categorizing error messages according to textual patterns and meaning.