Two-level utilization-based processor allocation for scheduling moldable jobs

2020 ◽  
Vol 76 (12) ◽  
pp. 10212-10239
Author(s):  
Ying-Jhih Wu ◽  
Shuo-Ting Yu ◽  
Kuan-Chou Lai ◽  
Amit Chhabra ◽  
Hsi-Ya Chang ◽  
...  
Keyword(s):  
2005 ◽  
Vol 16 (7) ◽  
pp. 599-611 ◽  
Author(s):  
J. Corbalan ◽  
X. Martorell ◽  
J. Labarta
Keyword(s):  

1994 ◽  
Vol 03 (01) ◽  
pp. 47-60
Author(s):  
R.A. McCONNELL ◽  
B.L. MENEZES

This article compares three techniques for allocating tasks in a mesh-based multi-computer. Tasks are expressed as rectangles of a certain width and height corresponding to the topology of processors desired. The task allocation problem, is thus a variant of the bin-packing problem, with one major difference: in the bin-packing problem one seeks to minimize the height of the bin, while here we seek to maximize the utilization of processors in a multicomputer. The three techniques compared are a classical level-by-level algorithm, a connectionist simulated annealing variant of the Hopfield network, and a genetic algorithm. An extension to the dynamic processor allocation problem is modeled by fixing some rectangles in place and packing the request rectangles in the residual space on the mesh; this corresponds to a pre-existing condition, i.e., some tasks have already been allocated to the Processor Mesh. Implementation and experimental results are presented.


2012 ◽  
Vol 58 (1) ◽  
pp. 9-14 ◽  
Author(s):  
Dawid Zydek ◽  
Grzegorz Chmaj ◽  
Alaa Shawky ◽  
Henry Selvaraj

Location of Processor Allocator and Job Scheduler and Its Impact on CMP PerformanceHigh Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.


1997 ◽  
Vol 8 (7) ◽  
pp. 712-726 ◽  
Author(s):  
V. Lo ◽  
K.J. Windisch ◽  
Wanqian Liu ◽  
B. Nitzberg

Algorithmica ◽  
2007 ◽  
Vol 50 (2) ◽  
pp. 279-298 ◽  
Author(s):  
Michael A. Bender ◽  
David P. Bunde ◽  
Erik D. Demaine ◽  
Sándor P. Fekete ◽  
Vitus J. Leung ◽  
...  

2019 ◽  
Vol 87 ◽  
pp. 77-86 ◽  
Author(s):  
J. Austin Ellis ◽  
Thomas M. Evans ◽  
Steven P. Hamilton ◽  
C.T. Kelley ◽  
Tara M. Pandya

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