Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors

Journal of Signal Processing Systems ◽

10.1007/s11265-008-0276-5 ◽

2008 ◽

Vol 57 (2) ◽

pp. 155-172

Author(s):

Anca M. Molnos ◽

Sorin D. Cotofana ◽

Marc J. M. Heijligers ◽

Jos T. J. van Eijndhoven

Keyword(s):

Chip Multiprocessors ◽

Cache Management ◽

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Compositional, dynamic cache management for embedded chip multiprocessors

2008 Design, Automation and Test in Europe ◽

10.1109/date.2008.4484810 ◽

2008 ◽

Author(s):

Anca M. Molnos ◽

Marc J.M. Heijligers ◽

Sorin D. Cotofana

Keyword(s):

Chip Multiprocessors ◽

Cache Management ◽

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Compositional, dynamic cache management for embedded chip multiprocessors

2008 Design, Automation and Test in Europe ◽

10.1145/1403375.1403615 ◽

2008 ◽

Author(s):

Anca M. Molnos ◽

Marc J. M. Heijligers ◽

Sorin D. Cotofana

Keyword(s):

Chip Multiprocessors ◽

Cache Management ◽

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A case for lifetime-aware task mapping in embedded chip multiprocessors

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES/ISSS '10 ◽

10.1145/1878961.1878987 ◽

2010 ◽

Author(s):

Adam S. Hartman ◽

Donald E. Thomas ◽

Brett H. Meyer

Keyword(s):

Chip Multiprocessors ◽

Task Mapping ◽

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Notice of Violation of IEEE Publication Principles: An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors

IEEE Transactions on Emerging Topics in Computing ◽

10.1109/tetc.2016.2563323 ◽

2019 ◽

pp. 1-1 ◽

Author(s):

Salman Onsori ◽

Arghavan Asad ◽

Kaamran Raahemifar ◽

Mahmood Fathy

Keyword(s):

Energy Efficient ◽

Chip Multiprocessors ◽

Memory Architecture ◽

Dark Silicon ◽

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Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors

IEEE Embedded Systems Letters ◽

10.1109/les.2012.2193553 ◽

2012 ◽

Vol 4 (2) ◽

pp. 41-44 ◽

Author(s):

Yong Zou ◽

Yi Xiang ◽

S. Pasricha

Keyword(s):

Chip Multiprocessors ◽

Network Interfaces ◽

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Write activity reduction on non-volatile main memories for embedded chip multiprocessors

ACM Transactions on Embedded Computing Systems ◽

10.1145/2442116.2442127 ◽

2013 ◽

Vol 12 (3) ◽

pp. 1-27 ◽

Author(s):

Jingtong Hu ◽

Chun Jason Xue ◽

Qingfeng Zhuge ◽

Wei-Che Tseng ◽

Edwin H.-M. Sha

Keyword(s):

Chip Multiprocessors ◽

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Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors

2017 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) ◽

10.1109/recosoc.2017.8016154 ◽

2017 ◽

Author(s):

Fatemeh Arezoomand ◽

Arghavan Asad ◽

Mahdi Fazeli ◽

Mahmood Fathy ◽

Farah Mohammadi

Keyword(s):

Chip Multiprocessors ◽

Energy Aware ◽

Cache Design ◽

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A leakage-aware L2 cache management technique for producer–consumer sharing in low-power chip multiprocessors

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2011.08.006 ◽

2011 ◽

Vol 71 (12) ◽

pp. 1545-1557 ◽

Author(s):

Hyunhee Kim ◽

Jihong Kim

Keyword(s):

Low Power ◽

Chip Multiprocessors ◽

Management Technique ◽

Cache Management ◽

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Multi-level on-chip memory hierarchy design for embedded chip multiprocessors

12th International Conference on Parallel and Distributed Systems - (ICPADS'06) ◽

10.1109/icpads.2006.66 ◽

2006 ◽

Author(s):

O. Ozturk ◽

M. Kandemir ◽

M.J. Irwin ◽

S. Tosun

Keyword(s):

Chip Multiprocessors ◽

Memory Hierarchy ◽

Multi Level ◽

On Chip ◽

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SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.14 ◽

2009 ◽

Author(s):

Lei Jin ◽

Sangyeun Cho

Keyword(s):

Chip Multiprocessors ◽

Management Approach ◽

Cache Management ◽

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