A leakage-aware L2 cache management technique for producer–consumer sharing in low-power chip multiprocessors

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2011.08.006 ◽

2011 ◽

Vol 71 (12) ◽

pp. 1545-1557 ◽

Author(s):

Hyunhee Kim ◽

Jihong Kim

Keyword(s):

Low Power ◽

Chip Multiprocessors ◽

Management Technique ◽

Cache Management ◽

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A low-power management technique for high-performance domino circuits

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) ◽

10.1109/aspdac.2011.5722313 ◽

2011 ◽

Author(s):

Yu-Tzu Tsai ◽

Cheng-Chih Tsai ◽

Cheng-An Chien ◽

Ching-Hwa Cheng ◽

Jiun-In Guo

Keyword(s):

Low Power ◽

Power Management ◽

High Performance ◽

Management Technique ◽

Domino Circuits

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Battery Management Technique to Reduce Standby Energy Consumption in Ultra-Low Power IoT and Sensory Applications

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2019.2940022 ◽

2020 ◽

Vol 67 (1) ◽

pp. 336-345 ◽

Author(s):

Mohsen Radfar ◽

Amir Nakhlestani ◽

Hoang Le Viet ◽

Aniruddha Desai

Keyword(s):

Energy Consumption ◽

Low Power ◽

Management Technique ◽

Battery Management ◽

Ultra Low Power

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Design of low power L2 cache architecture using partial way tag information

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922292 ◽

2014 ◽

Author(s):

A. Divya Jebaseeli ◽

M. Kiruba

Keyword(s):

Low Power ◽

Cache Architecture ◽

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TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors

Proceedings of the International Symposium on Low Power Electronics and Design ◽

10.1145/566408.566471 ◽

2002 ◽

Author(s):

Magnus Ekman ◽

Per Stenström ◽

Fredrik Dahlgren

Keyword(s):

Low Power ◽

Chip Multiprocessors ◽

Energy Reduction

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A Cache Management Technique Based on Eviction Cost Estimation for Heterogeneous Storage Devices

IEMEK Journal of Embedded Systems and Applications ◽

10.14372/iemek.2012.7.3.129 ◽

2012 ◽

Vol 7 (3) ◽

pp. 129-134

Author(s):

SeJin Park ◽

ChanIk Park

Keyword(s):

Cost Estimation ◽

Management Technique ◽

Cache Management ◽

Storage Devices

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Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors

Journal of Signal Processing Systems ◽

10.1007/s11265-008-0276-5 ◽

2008 ◽

Vol 57 (2) ◽

pp. 155-172

Author(s):

Anca M. Molnos ◽

Sorin D. Cotofana ◽

Marc J. M. Heijligers ◽

Jos T. J. van Eijndhoven

Keyword(s):

Chip Multiprocessors ◽

Cache Management ◽

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DHL‐cache: dynamic per history length adjustment for low‐power L2 cache

Electronics Letters ◽

10.1049/el.2016.1465 ◽

2016 ◽

Vol 52 (15) ◽

pp. 1297-1298

Author(s):

H.W. Joo ◽

E.Y. Chung

Keyword(s):

Low Power ◽

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Compositional, dynamic cache management for embedded chip multiprocessors

2008 Design, Automation and Test in Europe ◽

10.1109/date.2008.4484810 ◽

2008 ◽

Author(s):

Anca M. Molnos ◽

Marc J.M. Heijligers ◽

Sorin D. Cotofana

Keyword(s):

Chip Multiprocessors ◽

Cache Management ◽

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A Buffer Management Technique for Guaranteed Desired Communication Reliability and Low-Power in Wireless Sensor Networks

IEICE Transactions on Communications ◽

10.1587/transcom.e93.b.3522 ◽

2010 ◽

Vol E93-B (12) ◽

pp. 3522-3525 ◽

Author(s):

Dae-Young KIM ◽

Jinsung CHO ◽

Ben LEE

Keyword(s):

Wireless Sensor Networks ◽

Sensor Networks ◽

Low Power ◽

Buffer Management ◽

Wireless Sensor ◽

Management Technique ◽

Communication Reliability

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SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors

2009 18th International Conference on Parallel Architectures and Compilation Techniques ◽

10.1109/pact.2009.14 ◽

2009 ◽

Author(s):

Lei Jin ◽

Sangyeun Cho

Keyword(s):

Chip Multiprocessors ◽

Management Approach ◽

Cache Management ◽

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