DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing

2022 ◽  
Author(s):  
Chenglong Sun ◽  
Yiming Ouyang ◽  
Yingchun Lu
2017 ◽  
Vol 25 (3) ◽  
pp. 1126-1139 ◽  
Author(s):  
Karthi Duraisamy ◽  
Yuankun Xue ◽  
Paul Bogdan ◽  
Partha Pratim Pande

Author(s):  
Saliha Lakhdari ◽  
Fateh Boutekkouk

Designing sustainable and high-performance wireless multi-core chips requires a matchless tradeoff between many aspects including scalable and reliable architectures implementation which in its turn implies aware-wideband energy-efficient wireless interfaces and adopting innovative straightforward optimization approaches to achieve the optimal configuration with a minimal cost. This paper focuses on investigating various existing designs and methodologies for wireless network on chip (WiNoC) architectures, as well as the different emerging technologies and optimization tools for the design of a robust and reliable WiNoC infrastructure with a special focus on combinatorial optimization meta-heuristics.


IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Quoc-Tuan Vien ◽  
Michael Opoku Agyeman ◽  
Mallik Tatipamula ◽  
Huan X. Nguyen

2021 ◽  
Vol 2 ◽  
pp. 485-496
Author(s):  
Kasem Khalil ◽  
Omar Eldash ◽  
Ashok Kumar ◽  
Magdy Bayoumi

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