Test Time Reduction in Automated Test Equipment (ATE)-Based Mechanism of Network-on-Chip Communication Infrastructure

2015 ◽  
Vol 40 (11) ◽  
pp. 3197-3209
Author(s):  
Mona Soleymani ◽  
Midia Reshadi
Keyword(s):  
Network On Chip ◽  
Test Equipment ◽  
Test Time ◽  
Communication Infrastructure ◽  
Automated Test Equipment ◽  
Test Time Reduction ◽  
Automated Test ◽  
Time Reduction ◽  
On Chip

scholarly journals Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture

2005 ◽  
Author(s):  
A.M. Amory ◽  
M. Lubaszewski ◽  
F.G. Moraes ◽  
E.I. Moreno
Keyword(s):  
Network On Chip ◽  
Test Time ◽  
Multiple Processors ◽  
Test Time Reduction ◽  
Time Reduction ◽  
On Chip

scholarly journals A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs

2008 ◽  
Vol E91-D (10) ◽  
pp. 2428-2434
Author(s):  
H.-M. SHIEH ◽  
J.-F. LI
Keyword(s):  
System On Chip ◽  
Test Time ◽  
Compression Scheme ◽  
Code Compression ◽  
Test Time Reduction ◽  
Time Reduction ◽  
On Chip

scholarly journals Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

2021 ◽  
Vol 35 (3) ◽  
pp. 265-271
Author(s):  
Gokul Chandrasekaran ◽  
Gopinath Singaram ◽  
Rajkumar Duraisamy ◽  
Akash Sanjay Ghodake ◽  
Parthiban Kunnathur Ganesan
Keyword(s):  
Firefly Algorithm ◽  
Base Material ◽  
Test Time ◽  
Test Scheduling ◽  
Testing Time ◽  
Test Cost ◽  
Test Cost Reduction ◽  
Test Time Reduction ◽  
Time Reduction ◽  
On Chip

System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.

An Alternative to High-Temperature and Acid/Solvent-Based Methods for Removing Integrated Circuits from Ceramic or Other Problem Substrates

2005 ◽  
Author(s):  
Carl M. Nail
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Success Rate ◽  
Mechanical Damage ◽  
Test Equipment ◽  
High Success Rate ◽  
Automated Test Equipment ◽  
Removal Method ◽  
Automated Test ◽  
Conventional Methods

Abstract Dice must often be removed from their packages and reassembled into more suitable packages for them to be tested in automated test equipment (ATE). Removing bare dice from their substrates using conventional methods poses risks for chemical, thermal, and/or mechanical damage. A new removal method is offered using metallography-based and parallel polishing-based techniques to remove the substrate while exposing the die to minimized risk for damage. This method has been tested and found to have a high success rate once the techniques are learned.

Modular Automated Test Equipment (MATE) 390 Enhancement Program

2000 ◽  
Author(s):  
David R. Carey
Keyword(s):  
Test Equipment ◽  
Automated Test Equipment ◽  
Automated Test

Versuchszeit reduzieren - Möglichkeiten und Grenzen / Test Time Reduction - Chances and Limits

1998 ◽  
Vol 40 (6) ◽  
pp. 240-244
Author(s):  
H Zenner
Keyword(s):  
Test Time ◽  
Test Time Reduction ◽  
Time Reduction
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