On test time reduction using pattern overlapping, broadcasting and on-chip decompression

2012 ◽  
Author(s):  
Martin Chloupek ◽  
Ondrej Novak ◽  
Jiri Jenicek
Keyword(s):  
Test Time ◽  
Test Time Reduction ◽  
Time Reduction ◽  
On Chip

scholarly journals Test Scheduling and Test Time Reduction for SoC by Using Enhanced Firefly Algorithm

2021 ◽  
Vol 35 (3) ◽  
pp. 265-271
Author(s):  
Gokul Chandrasekaran ◽  
Gopinath Singaram ◽  
Rajkumar Duraisamy ◽  
Akash Sanjay Ghodake ◽  
Parthiban Kunnathur Ganesan
Keyword(s):  
Firefly Algorithm ◽  
Base Material ◽  
Test Time ◽  
Test Scheduling ◽  
Testing Time ◽  
Test Cost ◽  
Test Cost Reduction ◽  
Test Time Reduction ◽  
Time Reduction ◽  
On Chip

System-on-Chip (SoC) is an integration of electronic components and billions of transistors. Defects due to the base material is caused during the manufacturing of components. To overcome these issues testing of chips is necessary but total cost increases because of increasing test time. The main issues to be considered during testing of SoC are the time taken for testing and accessibility of core. Effective test scheduling should be done to minimize testing time. In this paper, an effective test scheduling mechanism to minimize testing time is proposed. The test time reduction causes test cost reduction. The Enhanced Firefly algorithm is used in this paper to minimize test time. Enhanced Firefly algorithm gives a better result than Ant colony and Firefly algorithms in terms of test time reduction thereby reduction test cost takes place.

2.2.1 Test time reduction by optimal test sequencing1

2006 ◽  
Vol 16 (1) ◽  
pp. 259-269 ◽  
Author(s):  
R. Boumen ◽  
I.S.M. de Jong ◽  
J.M. van de Mortel-Fronczak ◽  
J.E. Rooda
Keyword(s):  
Test Time ◽  
Optimal Test ◽  
Test Time Reduction ◽  
Time Reduction
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