A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

Design of a novel initialization circuit is presented in this paper. The initialization circuit is used to supply initialization current to the first test of phase change memory chip after delivery. Inhomogeneous crystalline grain sizes appear in phase change materials used in memory cells during manufacturing process. The crystalline phase with low resistance will convert to amorphous phase with high resistance after initialization, which is called RESET the memory cells to 0. Normal RESET operation current is not high enough to RESET great grain, which deteriorates bit yield of phase change memory chip. In comparison, the higher initialization current will increase bit yield observably.

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Correction: 12-state multi-level cell storage implemented in a 128 Mb phase change memory chip

Nanoscale ◽

10.1039/d1nr90100a ◽

2021 ◽

Author(s):

Zhitang Song ◽

Daolin Cai ◽

Yan Cheng ◽

Lei Wang ◽

Shilong Lv ◽

...

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Memory Chip ◽

Multi Level ◽

Change Memory ◽

Cell Storage

Correction for ‘12-state multi-level cell storage implemented in a 128 Mb phase change memory chip’ by Zhitang Song et al., Nanoscale, 2021, DOI: 10.1039/d1nr00100k.

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Ti–Sb–Te-Based Phase Change Memory Chip

Springer Theses - Ti-Sb-Te Phase Change Materials: Component Optimisation, Mechanism and Applications ◽

10.1007/978-981-10-4382-6_8 ◽

2017 ◽

pp. 113-124

Author(s):

Min Zhu

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Memory Chip ◽

Change Memory

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A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2010.2084491 ◽

2011 ◽

Vol 46 (1) ◽

pp. 52-63 ◽

Cited By ~ 22

Author(s):

Guido De Sandre ◽

Luca Bettini ◽

Alessandro Pirola ◽

Lionel Marmonier ◽

Marco Pasotti ◽

...

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Cmos Technology ◽

Change Memory

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Methods to speed up read operation in a 64 Mbit phase change memory chip

IEICE Electronics Express ◽

10.1587/elex.12.20150792 ◽

2015 ◽

Vol 12 (20) ◽

pp. 20150792-20150792 ◽

Cited By ~ 1

Author(s):

Qian Wang ◽

Xi Li ◽

Houpeng Chen ◽

Yifeng Chen ◽

Yueqing Wang ◽

...

Keyword(s):

Phase Change ◽

Phase Change Memory ◽

Memory Chip ◽

Read Operation ◽

Speed Up ◽

Change Memory

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Robust Simulations of Nanoscale Phase Change Memory: Dynamics and Retention

Nanomaterials ◽

10.3390/nano11112945 ◽

2021 ◽

Vol 11 (11) ◽

pp. 2945

Author(s):

Feilong Ding ◽

Deqi Dong ◽

Yihan Chen ◽

Xinnan Lin ◽

Lining Zhang

Keyword(s):

Phase Change ◽

Reaction Rate ◽

Phase Change Memory ◽

Simulation Method ◽

Cmos Technology ◽

Rate Theory ◽

Simulation Framework ◽

Reaction Rate Theory ◽

Dynamic Nucleation ◽

Change Memory

A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the non-isothermal conditions during PCM cell programming, an improved crystallization model was proposed that goes beyond the classical nucleation and growth model. With the above, the incubation period in which the cluster distributions reached their equilibrium was captured beyond the capability of simulations with a steady-state nucleation rate. The implications of the developed simulation method are discussed regarding PCM fast SET programming and retention. This work provides the possibility for further improvement of PCM and integration with CMOS technology.

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