Effect of power ratio of side/top heaters on the performance and growth of multi-crystalline silicon ingots

2022 ◽  
Vol 306 ◽  
pp. 130968
Author(s):  
Yinqiao Peng ◽  
Tianshu Feng ◽  
Jicheng Zhou
2013 ◽  
Vol 58 (2) ◽  
pp. 142-150 ◽  
Author(s):  
A.V. Sachenko ◽  
◽  
V.P. Kostylev ◽  
V.G. Litovchenko ◽  
V.G. Popov ◽  
...  

2020 ◽  
Vol 65 (3) ◽  
pp. 236
Author(s):  
R. M. Rudenko ◽  
O. O. Voitsihovska ◽  
V. V. Voitovych ◽  
M. M. Kras’ko ◽  
A. G. Kolosyuk ◽  
...  

The process of crystalline silicon phase formation in tin-doped amorphous silicon (a-SiSn) films has been studied. The inclusions of metallic tin are shown to play a key role in the crystallization of researched a-SiSn specimens with Sn contents of 1–10 at% at temperatures of 300–500 ∘C. The crystallization process can conditionally be divided into two stages. At the first stage, the formation of metallic tin inclusions occurs in the bulk of as-precipitated films owing to the diffusion of tin atoms in the amorphous silicon matrix. At the second stage, the formation of the nanocrystalline phase of silicon occurs as a result of the motion of silicon atoms from the amorphous phase to the crystalline one through the formed metallic tin inclusions. The presence of the latter ensures the formation of silicon crystallites at a much lower temperature than the solid-phase recrystallization temperature (about 750 ∘C). A possibility for a relation to exist between the sizes of growing silicon nanocrystallites and metallic tin inclusions favoring the formation of nanocrystallites has been analyzed.


2018 ◽  
Vol 1 (57) ◽  
pp. 23-30
Author(s):  
K. S. Elkin ◽  
◽  
A. D. Kolosov ◽  
S. A. Nebogin ◽  
◽  
...  
Keyword(s):  

Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.


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