Design and implementation of area efficient EAIC modulo adder

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

Design and implementation of area efficient, low power AMBA-APB Bridge for SoC

10.1109/icgccee.2014.6922239 ◽

2014 ◽

Author(s):

Abhijeet Paunikar ◽

Rohan Gavankar ◽

Nachiket Umarikar ◽

K. Sivasankaran

Keyword(s):

Low Power ◽

Design and Implementation of Low-Power, Area-Efficient Fir Filter using Different Distributed Arithmetic Techniques

Indian Journal of Science and Technology ◽

10.17485/ijst/2015/v8i21/79128 ◽

2015 ◽

Vol 8 (21) ◽

Author(s):

Pilli Ramesh ◽

P. Augusta Sophy Beulet

Keyword(s):

Low Power ◽

Fir Filter ◽

Distributed Arithmetic ◽

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) ◽

Design and Implementation of Sixteen-bit Low Power and Area Efficient Dadda Multiplier

10.1109/rteict46194.2019.9016834 ◽

2019 ◽

Cited By ~ 1

Author(s):

V Manu ◽

A M Vijaya Prakash ◽

Mohan U Chandra

Keyword(s):

Low Power ◽

Design and Implementation of High Speed and Area Efficient MAC Unit

International Journal of MC Square Scientific Research ◽

10.20894/ijmsr.117.009.001.014 ◽

2017 ◽

Vol 9 (1) ◽

pp. 117-129

Author(s):

M. Nivedha ◽

◽

V. Priyadharshini ◽

Keyword(s):

High Speed ◽

Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder

International Journal of Engineering Trends and Technology ◽

10.14445/22315381/ijett-v41p271 ◽

2016 ◽

Vol 41 (8) ◽

pp. 393-398

Author(s):

Ayushi Sharma ◽

◽

Ajit Singh

Keyword(s):

Vedic Multiplier ◽

Design and implementation of high performance and area efficient square architecture using Vedic Mathematics

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-019-01496-w ◽

2019 ◽

Vol 102 (3) ◽

pp. 501-506 ◽

Cited By ~ 1

Author(s):

Beechu Naresh Kumar Reddy

Keyword(s):

High Performance ◽

Vedic Mathematics ◽

FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation

2019 53rd Asilomar Conference on Signals, Systems, and Computers ◽

10.1109/ieeeconf44664.2019.9049071 ◽

2019 ◽

Cited By ~ 1

Author(s):

Ayan Palchaudhuri ◽

Anindya Sundar Dhar

Keyword(s):

Design and implementation of area efficient multi-ported memories with write conflict resolution

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2015.7282041 ◽

2015 ◽

Author(s):

Akshata Anil Muddebihal ◽

Carla Purdy

Keyword(s):

Conflict Resolution ◽

Design and implementation of modified iterative logarithmic multiplier for low-power and area-efficient applications

IOSR Journal of Electrical and Electronics Engineering ◽

10.9790/1676-09153445 ◽

2014 ◽

Vol 9 (1) ◽

pp. 34-45 ◽

Cited By ~ 2

Author(s):

Rohan Appasaheb Borgalli ◽

◽

Hari Pratap Gautam ◽

Winner George Parayil

Keyword(s):

Low Power ◽

Design and implementation of a low power and area efficient sequential multiplier

Communication and Computing Systems ◽

10.1201/9781315364094-110 ◽

2016 ◽

Author(s):

Mohit Kumar ◽

Nitin Dhaka ◽

Rohit Toliya ◽

S Yadav

Keyword(s):

Low Power ◽