Design and Implementation of High Speed and Area Efficient MAC Unit

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings ◽

Design and implementation of a high-speed and area-efficient viterbi decoder

10.1109/icsict.2006.306631 ◽

2006 ◽

Cited By ~ 1

Author(s):

Hao Yang ◽

Xiao-lang Yan

Keyword(s):

High Speed ◽

Viterbi Decoder ◽

Design and implementation of a Hybrid High Speed Area Efficient Parallel Prefix Adder in an FPGA

International Journal of Computer Applications ◽

10.5120/9246-3410 ◽

2012 ◽

Vol 58 (1) ◽

pp. 17-21 ◽

Cited By ~ 1

Author(s):

S. V.Padmajarani ◽

M. Muralidhar

Keyword(s):

High Speed ◽

Parallel Prefix ◽

Prefix Adder ◽

International Journal of Innovative Research in Computer and Communication Engineering ◽

Design and Implementation of High Speed 64-Bit Multiply and Accumulator Unit Using FPGA

10.15680/ijircce.2015.0305022 ◽

2015 ◽

Vol 03 (05) ◽

pp. 3889-3896 ◽

Cited By ~ 1

Author(s):

Dipika Chauhan, Prof. Kinjal va gadia, Prof. Kirit Patel

Keyword(s):

High Speed ◽

Design And Implementation

The design and implementation of high-speed real-time optical OFDM transmission based on an IMDD system

International Workshop on Communication Technology 2013 ◽

10.2495/cecnet130211 ◽

2014 ◽

Author(s):

Luo wei Zhang

Keyword(s):

Real Time ◽

High Speed ◽

Optical Ofdm

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

10.1109/edssc.2019.8754423 ◽

2019 ◽

Author(s):

Diptesh Datta ◽

Piyush Dewangan ◽

Neelam Surana ◽

Joycee Mekie

Keyword(s):

High Speed ◽

Content Addressable Memory ◽

Ternary Content Addressable Memory ◽

2020 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering (WIECON-ECE) ◽

Design and Implementation of High-speed Low Voltage 4x4 Vedic Convolutor

10.1109/wiecon-ece52138.2020.9398039 ◽

2020 ◽

Author(s):

Shreya Bhattacharyya ◽

Souvik Majumder ◽

Papiya Debnath ◽

Manash Chanda

Keyword(s):

High Speed ◽

Low Voltage ◽

Design And Implementation

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Materials Today Proceedings ◽

10.1016/j.matpr.2020.07.677 ◽

2020 ◽

Author(s):

A. Arunkumar Gudivada ◽

K. Jayaram Kumar ◽

Srinivasa Rao Jajula ◽

Durga Prasad Siddani ◽

Praveen Kumar Poola ◽

...

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

High Speed ◽

Quantum Dot Cellular Automata ◽

Wallace Tree ◽

Wallace Tree Multiplier ◽

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

High-speed area-efficient recursive DFT/IDFT architectures

10.1109/iscas.2004.1328757 ◽

2004 ◽

Author(s):

Lan-Da Van ◽

Chih-Chyau Yang

Keyword(s):

High Speed ◽

Design and implementation of a high speed Serial Peripheral Interface

2014 International Conference on Advances in Electrical Engineering (ICAEE) ◽

10.1109/icaee.2014.6838431 ◽

2014 ◽

Cited By ~ 3

Author(s):

Anand N ◽

George Joseph ◽

Suwin Sam Oommen ◽

R Dhanabal

Keyword(s):

High Speed ◽

Serial Peripheral Interface